EP 0640261 A1 19950301 - DATA TRANSMISSION DELAYING CIRCUIT USING TIME-MULTIPLEXED LATCH ENABLE SIGNALS.
Title (en)
DATA TRANSMISSION DELAYING CIRCUIT USING TIME-MULTIPLEXED LATCH ENABLE SIGNALS.
Title (de)
DATENÜBERTRAGUNGSVERZÖGERUNGSSCHALTUNG MIT ZEITMULTIPLEXIERTEN VERRIEGELUNGSSCHALTUNGSFREIGABESIGNALEN.
Title (fr)
CIRCUIT RETARDANT LA TRANSMISSION DE DONNEES A L'AIDE DE SIGNAUX DE VALIDATION DE VERROUILLAGE MULTIPLEXES DANS LE TEMPS.
Publication
Application
Priority
US 9204080 W 19920514
Abstract (en)
[origin: WO9323937A1] A digital signal phase adjustment circuit adjusts the phase of a data signal in relation to a first local clock signal having a frequency of f. Also provided is a second local clock signal with a frequency of Nf, where N is a positive integer greater than 1. An N-bit shift register (120), clocked by the second local clock signal, generates N phase signals that are enabled in rotating sequential order during non-overlapping time intervals. One of the N phase signals is selected by a multiplexer (130) and used as the enable control signal for a data sampling circuit that is clocked by the second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting the data signal with a selected phase relative to the first clock signal.
IPC 1-7
IPC 8 full level
H03K 5/135 (2006.01); H03D 3/24 (2006.01); H03L 7/00 (2006.01); H04L 7/02 (2006.01); H04L 7/027 (2006.01); H04L 7/033 (2006.01)
CPC (source: EP)
H03L 7/00 (2013.01); H04L 7/0338 (2013.01)
Designated contracting state (EPC)
DE GB
DOCDB simple family (publication)
WO 9323937 A1 19931125; EP 0640261 A1 19950301; EP 0640261 A4 19950405
DOCDB simple family (application)
US 9204080 W 19920514; EP 92913469 A 19920514