EP 0650127 A2 19950426 - Digital signal processing circuit.
Title (en)
Digital signal processing circuit.
Title (de)
Digitale Signalverarbeitungseinrichtung.
Title (fr)
Circuit de traitement de signaux numériques.
Publication
Application
Priority
JP 26282093 A 19931020
Abstract (en)
A digital signal processing circuit, which is configured by a digital signal processor (i.e., DSP), comprises at least a data memory (DR), a coefficient memory (CR), a calculation portion (MX) and an interpolation portion (INT). The data memory stores a plurality of digital data which are sequentially supplied thereto, while the coefficient memory stores a plurality of coefficients in connection with the plurality of digital data. The calculation portion performs a specific calculation (e.g., multiplication), using the coefficient, on the digital data. When a new coefficient is given with respect to one of the coefficients designated, the interpolation portion performs interpolation processing on the designated coefficient so as to successively shift it to the new coefficient. The coefficient successively shifted is stored in the coefficient memory. Hence, the calculation portion performs the calculation, using the coefficient successively shifted, on the digital data.
IPC 1-7
IPC 8 full level
H03H 21/00 (2006.01); G06F 17/15 (2006.01); G06F 17/17 (2006.01); H03H 17/00 (2006.01); H03H 17/02 (2006.01)
CPC (source: EP US)
G06F 17/15 (2013.01 - EP US); G06F 17/17 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0650127 A2 19950426; EP 0650127 A3 19950607; EP 0650127 B1 20020306; DE 69430034 D1 20020411; DE 69430034 T2 20030130; JP H07122973 A 19950512; US 5636153 A 19970603
DOCDB simple family (application)
EP 94116412 A 19941018; DE 69430034 T 19941018; JP 26282093 A 19931020; US 32599694 A 19941019