EP 0698294 A1 19960228 - LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE
Title (en)
LOGICAL THREE-DIMENSIONAL INTERCONNECTIONS BETWEEN INTEGRATED CIRCUIT CHIPS USING A TWO-DIMENSIONAL MULTI-CHIP MODULE PACKAGE
Title (de)
DREIDIMENSIONALE LOGISCHE VERBINDUNGEN ZWISCHEN INTEGRIERTEN SCHALTUNGSCHIPS MIT ZWEIDIMENSIONALER MULTICHIP-MODULVERPACKUNG
Title (fr)
INTERCONNEXIONS LOGIQUES TRIDIMENSIONNELLES ENTRE DES PUCES DE CIRCUITS INTEGRES UTILISANT UN BOITIER BIDIMENSIONNNEL POUR UN MODULE MULTIPUCE
Publication
Application
Priority
- US 9500796 W 19950120
- US 21314694 A 19940315
Abstract (en)
[origin: WO9525348A1] A high-capacity gate array which incorporates an effectively three-dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three-dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three-dimensional interconnect network from a two-dimensional arrangement of arrays or chips in an MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.
IPC 1-7
IPC 8 full level
H01L 23/538 (2006.01); H01L 25/065 (2006.01); H03K 19/177 (2006.01)
CPC (source: EP KR)
H01L 23/5385 (2013.01 - EP); H01L 23/5386 (2013.01 - EP); H01L 25/065 (2013.01 - KR); H01L 25/0652 (2013.01 - EP); H03K 19/17704 (2013.01 - EP); H01L 2924/0002 (2013.01 - EP)
C-Set (source: EP)
Citation (search report)
See references of WO 9525348A1
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
WO 9525348 A1 19950921; EP 0698294 A1 19960228; KR 100360074 B1 20030124; KR 960702943 A 19960523
DOCDB simple family (application)
US 9500796 W 19950120; EP 95908601 A 19950120; KR 19950705101 A 19951115