EP 0698312 A1 19960228 - TILE BASED ARCHITECTURE FOR FPGA
Title (en)
TILE BASED ARCHITECTURE FOR FPGA
Title (de)
AUS BASISMODULEN AUFGEBAUTE FPGA-ARCHITEKTUR
Title (fr)
ARCHITECTURE EN TUILES JUXTAPOSEES POUR MATRICE DE PORTES PROGRAMMABLES PAR L'UTILISATEUR
Publication
Application
Priority
- US 9501554 W 19950207
- US 19691494 A 19940215
- US 22213894 A 19940401
Abstract (en)
[origin: WO9522205A1] An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
IPC 1-7
IPC 8 full level
H03K 19/177 (2006.01)
CPC (source: EP)
H03K 19/17704 (2013.01); H03K 19/17796 (2013.01)
Citation (search report)
See references of WO 9522205A1
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
WO 9522205 A1 19950817; EP 0698312 A1 19960228; JP 3547446 B2 20040728; JP H08509344 A 19961001
DOCDB simple family (application)
US 9501554 W 19950207; EP 95909504 A 19950207; JP 52129595 A 19950207