Global Patent Index - EP 0704077 B1

EP 0704077 B1 2000-10-04 - DATA PROCESSING APPARATUS FOR SIMULATING ASYNCHRONOUS LOGIC CIRCUITS

Title (en)

DATA PROCESSING APPARATUS FOR SIMULATING ASYNCHRONOUS LOGIC CIRCUITS

Title (de)

DATENVERARBEITUNGSGERÄT ZUR SIMULATION VON ASYNCHRONEN LOGISCHEN SCHALTKREISEN

Title (fr)

APPAREIL DE TRAITEMENT DE DONNEES POUR LA SIMULATION DE CIRCUITS ASYNCHRONES LOGIQUES

Publication

EP 0704077 B1 (EN)

Application

EP 95910711 A

Priority

  • GB 9406931 A
  • IB 9500192 W

Abstract (en)

[origin: WO9527952A2] A data processing apparatus comprises means for modelling asynchronous logic circuits as a plurality of circuit elements the functions of which are governed by a set of rules each defining a response to a given condition. For elements functioning as registers (x, b) a "copy" rule may be applied to at least one of them (x) with the associated response to the copy rule being the change of the output state of that register element (218, 220) in response to a change of output state of a further register element (b) identified by the copy rule. A further "identify" rule (200-226) may be applied to pairs of the register elements (x, b), according to which rule copy rules are applied to each element of the pair (216-222) in respect of changes of output state of the other. The apparatus may be arranged to model a number of asynchronous logic circuits in a working memory area with interconnections between such circuits being established by use of the identify rule.

IPC 1-7 (main, further and additional classification)

G06F 17/50

IPC 8 full level (invention and additional information)

G06F 11/25 (2006.01); G06F 17/50 (2006.01)

CPC (invention and additional information)

G06F 17/5022 (2013.01); Y10S 706/92 (2013.01); Y10S 706/921 (2013.01)

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

WO 9527952 A2 19951019; WO 9527952 A3 19951116; DE 69519010 D1 20001109; DE 69519010 T2 20010510; EP 0704077 A2 19960403; EP 0704077 B1 20001004; GB 9406931 D0 19940601; JP H08512160 A 19961217; US 5768161 A 19980616

INPADOC legal status


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2002-01-01 [REG GB IF02] EUROPEAN PATENT IN FORCE AS OF 2002-01-01

2001-09-19 [26N] NO OPPOSITION FILED

2000-12-15 [ET] FR: TRANSLATION FILED

2000-12-07 [ITF] IT: TRANSLATION FOR A EP PATENT FILED

- Owner name: BARZANO' E ZANARDO ROMA S.P.A.

2000-11-09 [REF] CORRESPONDS TO:

- Document: DE 69519010 20001109

2000-10-04 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: B1

- Designated State(s): DE FR GB IT

2000-01-19 [17Q] FIRST EXAMINATION REPORT

- Effective date: 19990625

1999-11-24 [RIC1] CLASSIFICATION (CORRECTION)

- Free text: 6G 06F 17/50 A

1999-11-24 [RTI1] TITLE (CORRECTION)

- Free text: DATA PROCESSING APPARATUS FOR SIMULATING ASYNCHRONOUS LOGIC CIRCUITS

1999-08-11 [17Q] FIRST EXAMINATION REPORT

- Effective date: 19990625

1996-06-19 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 19960419

1996-04-24 [AK] DESIGNATED CONTRACTING STATES:

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1996-04-03 [AK] DESIGNATED CONTRACTING STATES:

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1996-04-03 [AK] DESIGNATED CONTRACTING STATES:

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