EP 0708968 A1 19960501 - NON-VOLATILE MEMORY
Title (en)
NON-VOLATILE MEMORY
Title (de)
NICHTFLÜCHTIGER SPEICHER
Title (fr)
MEMOIRE REMANENTE
Publication
Application
Priority
- US 9407403 W 19940630
- US 9223393 A 19930715
Abstract (en)
[origin: WO9502883A1] A ferroelectric, non-volatile memory (336) includes a constant voltage source (85), a bit line (79), a memory cell (70) having a first ferroelectric capacitor (76) connected between the bit line (79) and the constant voltage source (85), a source (105) of a reference voltage, and a latch (74) connected between the bit line (79) and the reference voltage source (105). The latch (74) drives the bit line (79) to the same logic state as the ferroelectric capacitor (76) to read and rewrite the capacitor (76) in a single operation. The reference voltage is between QI/CD and QSW/CD + QI/CD, where QI is the linear capacitance of said first ferroelectric capacitor (76), CD is the capacitance of said bit line (79), and QSW is the switching charge of said first ferroelectric capacitor (76). In one embodiment, the reference voltage is provided by a ferroelectric dummy capacitor (141) having an area smaller than the area of the first capacitor (128) but greater than 1/2 the area of the first capacitor (128).
IPC 1-7
IPC 8 full level
G11C 11/22 (2006.01); G11C 11/41 (2006.01); G11C 17/04 (2006.01); H01L 27/10 (2006.01)
CPC (source: EP KR US)
G11C 11/22 (2013.01 - EP KR US)
Citation (search report)
See references of WO 9502883A1
Designated contracting state (EPC)
DE
DOCDB simple family (publication)
WO 9502883 A1 19950126; EP 0708968 A1 19960501; JP H09500475 A 19970114; KR 100345892 B1 20021122; KR 960704321 A 19960831; US 5406510 A 19950411
DOCDB simple family (application)
US 9407403 W 19940630; EP 94920833 A 19940630; JP 50458795 A 19940630; KR 19960700188 A 19960115; US 9223393 A 19930715