EP 0745288 B1 20000517 - PHASE-LOCKED LOOP FOR SIGNALS HAVING RECTANGULAR WAVEFORMS
Title (en)
PHASE-LOCKED LOOP FOR SIGNALS HAVING RECTANGULAR WAVEFORMS
Title (de)
PLL FÜR RECHTECKSIGNALE
Title (fr)
BOUCLE A PHASE ASSERVIE POUR SIGNAUX A FORMES D'ONDES RECTANGULAIRES
Publication
Application
Priority
- NL 9500422 W 19951215
- NL 9402129 A 19941215
- NL 9500491 A 19950313
Abstract (en)
[origin: US5710526A] PCT No. PCT/NL95/00422 Sec. 371 Date Aug. 15, 1996 Sec. 102(e) Date Aug. 15, 1996 PCT Filed Dec. 15, 1995 PCT Pub. No. WO96/19043 PCT Pub. Date Jun. 20, 1996Phase-locked loop (for signals having rectangular waveforms, comprising, in series, a phase detector, a control signal generator circuit having a loop filter, a controlled oscillator and an auxiliary circuit. The detector recieves a reference signal having a reference frequency from a reference source as first input signal. The detector recieves second and third input signals from the auxiliary circuit. The reference signal and the second input signal are compared by a first logic combination function to deliver a second combination signal. The second and third input signals are compared by a second logic combination function to deliver a second combination signal. The second and third input signals are such that, in the locked state of the loop, the frequency of the second input signal is equal to the reference fequency and the frequency of the second combination signal is equal to twice the reference frequency and the duty cycle of the second combination signal differs from the duty cycle of the reference signal. The difference between the two combination signals is delivered to the control signal generator circuit. For a frequency difference between the first and second input signals of the detector, the control signal generator circuit controls the oscillator so as to set the oscillator frequency in a direction towards an extreme oscillator frequency. If the loop does not lock while traversing this path, the control signal generator circuit will adjust the loop and control the oscillator in such a way that the oscillator fequency is set in the opposite direction towards a second extreme frequency. The two extreme oscillator frequencies are chosen below and above the desired oscillator frequency, respectively.
IPC 1-7
IPC 8 full level
H03L 7/085 (2006.01); H03L 7/12 (2006.01); H03L 7/191 (2006.01)
CPC (source: EP US)
H03L 7/085 (2013.01 - EP US); H03L 7/12 (2013.01 - EP US); H03L 7/191 (2013.01 - EP US)
Designated contracting state (EPC)
CH DE FR GB LI NL SE
DOCDB simple family (publication)
US 5710526 A 19980120; AU 4124496 A 19960703; DE 69517016 D1 20000621; DE 69517016 T2 20000914; EP 0745288 A1 19961204; EP 0745288 B1 20000517; NL 9500491 A 19960201; WO 9619043 A1 19960620
DOCDB simple family (application)
US 69328196 A 19960815; AU 4124496 A 19951215; DE 69517016 T 19951215; EP 95939427 A 19951215; NL 9500422 W 19951215; NL 9500491 A 19950313