EP 0746108 A2 19961204 - High-speed synchronous counter circuitry
Title (en)
High-speed synchronous counter circuitry
Title (de)
Schaltung für schnellen Synchronzähler
Title (fr)
Circuit de compteur synchrone à grande vitesse
Publication
Application
Priority
US 44946195 A 19950524
Abstract (en)
Digital counter register stages RCRG(N) are constructed as two-to-one mux registers, each employing a multiplexer stage (113) having first, second, and third inputs (S0, I0, I1) and an output (116) connected to the switching signal input (D) of a D-type flip-flop (15), whose Q output comprises a first input (I1) to the multiplexer stage (113). An inverter buffer (19) is associated with each register stage (RCRG(N)) and has an input connected to the output (Q) of said D-type flip-flop (115) and an output connected to the second input (I0) of the multiplexer stage (RCRG(N)) and fed forward to a NOR gate (21) associated with each subsequent register stage (RCRG(N)). <IMAGE>
IPC 1-7
IPC 8 full level
H03K 23/00 (2006.01); H03K 23/40 (2006.01); H03K 23/50 (2006.01)
CPC (source: EP KR US)
H03K 23/00 (2013.01 - KR); H03K 23/50 (2013.01 - EP US)
Designated contracting state (EPC)
CH DE ES FR GB IT LI
DOCDB simple family (publication)
EP 0746108 A2 19961204; EP 0746108 A3 19980211; EP 0746108 B1 20010829; CA 2175614 A1 19961115; CA 2175614 C 20001031; DE 69614763 D1 20011004; DE 69614763 T2 20020704; ES 2159687 T3 20011016; IL 118095 A0 19960912; IL 118095 A 19991028; JP 3247609 B2 20020121; JP H09107284 A 19970422; KR 100214399 B1 19990802; KR 960043531 A 19961223; US 5943386 A 19990824
DOCDB simple family (application)
EP 96303243 A 19960509; CA 2175614 A 19960502; DE 69614763 T 19960509; ES 96303243 T 19960509; IL 11809595 A 19960501; IL 11809596 A 19960501; JP 13018796 A 19960524; KR 19960017375 A 19960522; US 44946195 A 19950524