EP 0772821 B1 20021009 - TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION
Title (en)
TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION
Title (de)
MARKIERTER VORAUSLADUNGSABSTAND-UND BEFEHLSDEKODER VON VARIABLER LÄNGE, BEFEHLSSÄTZE UND IHRE VERWENDUNGSWEISE
Title (fr)
DISPOSITIF DE PREEXTRACTION MARQUE ET DECODEUR D'INSTRUCTIONS POUR INSTRUCTIONS DE LONGUEUR VARIABLE ET PROCEDE DE MISE EN UVRE
Publication
Application
Priority
- US 9607101 W 19960516
- US 44556395 A 19950526
Abstract (en)
[origin: WO9637829A1] A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.
IPC 1-7
IPC 8 full level
CPC (source: EP KR US)
G06F 9/30149 (2013.01 - EP KR US); G06F 9/3802 (2013.01 - EP US); G06F 9/3814 (2013.01 - EP KR US); G06F 9/3816 (2013.01 - EP KR US); G06F 9/3867 (2013.01 - EP KR US); G06F 9/3863 (2013.01 - KR)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
WO 9637829 A1 19961128; DE 69624195 D1 20021114; DE 69624195 T2 20030703; EP 0772821 A1 19970514; EP 0772821 B1 20021009; KR 970705079 A 19970906; US 6237074 B1 20010522
DOCDB simple family (application)
US 9607101 W 19960516; DE 69624195 T 19960516; EP 96915866 A 19960516; KR 19970700546 A 19970127; US 44556395 A 19950526