EP 0776010 A3 19981125 - Improvements in or relating to integrated circuits
Title (en)
Improvements in or relating to integrated circuits
Title (de)
Verbesserungen an oder in Bezug auf integrierte Schaltungen
Title (fr)
Améliorations relatives à des circuits intégrés
Publication
Application
Priority
US 56022995 A 19951121
Abstract (en)
[origin: EP0776010A2] The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pules from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 11/41 (2006.01); G11C 7/22 (2006.01); G11C 11/409 (2006.01)
CPC (source: EP KR US)
G11C 7/22 (2013.01 - EP US); G11C 11/40 (2013.01 - KR)
Citation (search report)
- [Y] US 4718043 A 19880105 - AKATSUKA YASUO [JP]
- [Y] US 4972374 A 19901120 - WANG KARL L [US], et al
- [A] EP 0527015 A2 19930210 - AMERICAN TELEPHONE & TELEGRAPH [US]
- [A] PATENT ABSTRACTS OF JAPAN vol. 095, no. 001 28 February 1995 (1995-02-28)
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 0776010 A2 19970528; EP 0776010 A3 19981125; JP 2007265601 A 20071011; JP 4443583 B2 20100331; JP H09231763 A 19970905; KR 100431479 B1 20040818; KR 970029787 A 19970626; TW 326571 B 19980211; US 5668769 A 19970916
DOCDB simple family (application)
EP 96308453 A 19961121; JP 2007098549 A 20070404; JP 31099196 A 19961121; KR 19960055541 A 19961120; TW 86103812 A 19970326; US 56022995 A 19951121