Global Patent Index - EP 0790708 A3

EP 0790708 A3 19990728 - Interpolating digital to analog converter architecture for improved spurious signal suppression

Title (en)

Interpolating digital to analog converter architecture for improved spurious signal suppression

Title (de)

Interpolierende Digital-Analog-Wandler-Architektur zur verbesserten Störsignalunterdrückung

Title (fr)

Architecture de conversion numérique-analogique améliorant l'élimination de signaux parasites

Publication

EP 0790708 A3 19990728 (EN)

Application

EP 97101555 A 19970131

Priority

US 60140196 A 19960214

Abstract (en)

[origin: EP0790708A2] A digital-to-analog conversion method and interpolating digital-to-analog converter (20) for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage (22) converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage (26) converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output (28) to an interpolation stage (30) which provides an interpolated output (32) at an interpolation output rate. A feedback circuit (34) provides the interpolated output to an input of the second conversion stage (26). <IMAGE>

IPC 1-7

H03M 1/08

IPC 8 full level

H03M 1/08 (2006.01); H03M 1/68 (2006.01); H03M 1/80 (2006.01)

CPC (source: EP KR US)

H03M 1/0863 (2013.01 - EP US); H03M 1/66 (2013.01 - KR); H03M 1/68 (2013.01 - EP US); H03M 1/804 (2013.01 - EP US)

Citation (search report)

  • [AD] US 5327092 A 19940705 - INOGAI KAZUNORI [JP], et al
  • [AD] GREGORIAN R: "High-resolution switched-capacitor D/A converter", MICROELECTRONICS JOURNAL, MARCH-APRIL 1981, UK, vol. 12, no. 2, ISSN 0026-2692, pages 10 - 13, XP002104001

Designated contracting state (EPC)

DE FR GB IT

DOCDB simple family (publication)

EP 0790708 A2 19970820; EP 0790708 A3 19990728; EP 0790708 B1 20010808; CN 1168570 A 19971224; DE 69705976 D1 20010913; DE 69705976 T2 20020404; KR 970063948 A 19970912; TW 341009 B 19980921; US 5798724 A 19980825

DOCDB simple family (application)

EP 97101555 A 19970131; CN 97102429 A 19970214; DE 69705976 T 19970131; KR 19970004549 A 19970214; TW 86101214 A 19970201; US 60140196 A 19960214