Global Patent Index - EP 0804765 A1

EP 0804765 A1 19971105 - ERROR DETECTION AND ERROR ELIMINATION IN A SERIAL DATA BUS SYSTEM

Title (en)

ERROR DETECTION AND ERROR ELIMINATION IN A SERIAL DATA BUS SYSTEM

Title (de)

FEHLERERKENNUNG UND FEHLERBESEITIGUNG BEI EINEM SERIELLEN DATENBUSSYSTEM

Title (fr)

PROCEDE DE DETECTION ET D'ELIMINATION D'ERREURS DANS UN SYSTEME DE BUS DE DONNEES SERIE

Publication

EP 0804765 A1 19971105 (DE)

Application

EP 96900959 A 19960116

Priority

  • DE 19501800 A 19950121
  • EP 9600150 W 19960116

Abstract (en)

[origin: DE19501800A1] The invention concerns a process which involves testing the SDA line (3) after a reset and is intended for use with a serial data bus with master (2) and slave (4) systems, preferably an I<2>C bus with a microcontroller and (for example) E<2>PROM. If the SDA line is at low potential, an error is recognised and eliminated by running a sub-program.

IPC 1-7

G06F 13/42

IPC 8 full level

G06F 13/38 (2006.01); G06F 13/00 (2006.01); G06F 13/42 (2006.01)

CPC (source: EP KR)

G06F 13/42 (2013.01 - KR); G06F 13/423 (2013.01 - EP)

Citation (search report)

See references of WO 9622572A1

Designated contracting state (EPC)

DE FR GB IT SE

DOCDB simple family (publication)

DE 19501800 A1 19960725; DE 59600992 D1 19990128; EP 0804765 A1 19971105; EP 0804765 B1 19981216; JP H11502643 A 19990302; KR 19980701425 A 19980515; WO 9622572 A1 19960725

DOCDB simple family (application)

DE 19501800 A 19950121; DE 59600992 T 19960116; EP 9600150 W 19960116; EP 96900959 A 19960116; JP 52203096 A 19960116; KR 19970704815 A 19970715