EP 0811937 A3 19980729 - Automatically prefetching data in a computer system
Title (en)
Automatically prefetching data in a computer system
Title (de)
Automatische Datenvorausladung in einem Rechnersystem
Title (fr)
Préextraction automatique de données dans un système d'ordinateur
Publication
Application
Priority
US 65849696 A 19960605
Abstract (en)
[origin: EP0811937A2] A computer system includes a memory device on the first data bus, a requesting device that initiates a delayed memory read transaction on a second data bus, and a bridge device that delivers the delayed memory read transaction to the first data bus and receives from the first data bus completion data requested in the memory read transaction. The bridge device includes a data storage buffer that stores the completion data, and a buffer management element that automatically requests from the memory device additional data to be placed in the data storage buffer. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 13/36 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2006.01); G06F 13/40 (2006.01)
CPC (source: EP US)
G06F 12/0215 (2013.01 - EP US); G06F 13/4054 (2013.01 - EP US)
Citation (search report)
- [X] EP 0629956 A2 19941221 - IBM [US]
- [A] WO 9408296 A1 19940414 - COMPAQ COMPUTER CORP [US]
- [X] WANG K ET AL: "DESIGNING THE MPC105 PCI BRIDGE/MEMORY CONTROLLER", IEEE MICRO, vol. 15, no. 2, 1 April 1995 (1995-04-01), pages 44 - 49, XP000499004
- [X] "BRIDGE CHIPS HELP CONNECT HOST AND EXPANSION BUSES TO THE PCI BUS", EDN ELECTRICAL DESIGN NEWS, vol. 40, no. 3, 2 February 1995 (1995-02-02), pages 77 - 80, 82, XP000507379
Designated contracting state (EPC)
AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
EP 0811937 A2 19971210; EP 0811937 A3 19980729; EP 0811937 B1 20050119; DE 69732268 D1 20050224; DE 69732268 T2 20050630; JP H10187597 A 19980721; US 6075929 A 20000613
DOCDB simple family (application)
EP 97303808 A 19970604; DE 69732268 T 19970604; JP 16207597 A 19970605; US 65849696 A 19960605