EP 0811980 A2 19971210 - Low voltage bootstrapping circuit
Title (en)
Low voltage bootstrapping circuit
Title (de)
Spannungserhöhungsschaltung für niedrige Spannung
Title (fr)
Circuit élévateur de tension pour faible tension
Publication
Application
Priority
US 66303296 A 19960607
Abstract (en)
A bootstrap circuit suitable for use in driving the word line of a FRAM TM memory circuit is energized by a VDD power supply voltage. The bootstrap circuit includes a first N-channel MOS transistor wherein the source/drain forms the input of the circuit. A second N-channel MOS transistor is included wherein one of the source/drains receives a clock signal, and the other source/drain forms the output, which drives the word line. The gate of the second transistor is coupled to the other source/drain of the first transistor. The bootstrap circuit includes further circuitry for generating a voltage greater than the VDD power supply voltage that is coupled to the gate of the first transistor. A capacitor or capacitor-connected transistor is coupled between the input and the gate of the first transistor, and a third transistor has one source/drain coupled to the gate of the first transistor, and the other source/drain receives a control signal, and the gate is coupled to the VDD power supply. The bootstrap circuit is operational even for VDD power supply voltages less than or equal to 3.3 volts. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 14/00 (2006.01); G11C 8/08 (2006.01); G11C 11/22 (2006.01); G11C 11/407 (2006.01); G11C 11/408 (2006.01)
CPC (source: EP US)
G11C 8/08 (2013.01 - EP US); G11C 11/22 (2013.01 - EP US); G11C 11/4085 (2013.01 - EP US)
Designated contracting state (EPC)
AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
EP 0811980 A2 19971210; EP 0811980 A3 19990609; JP H1092176 A 19980410; US 5999461 A 19991207
DOCDB simple family (application)
EP 97303887 A 19970605; JP 15118997 A 19970609; US 66303296 A 19960607