EP 0843843 B1 19991103 - BUFFER CIRCUIT ON A MODULE
Title (en)
BUFFER CIRCUIT ON A MODULE
Title (de)
AUF EINER BAUGRUPPE ANGEORDNETE PUFFERSCHALTUNG
Title (fr)
CIRCUIT TAMPON MONTE SUR UN MODULE
Publication
Application
Priority
- DE 9601367 W 19960724
- DE 19529718 A 19950811
Abstract (en)
[origin: US5927218A] PCT No. PCT/DE96/01367 Sec. 371 Date Jun. 24, 1998 Sec. 102(e) Date Jun. 24, 1998 PCT Filed Jul. 24, 1996 PCT Pub. No. WO97/07442 PCT Pub. Date Feb. 27, 1997A buffer circuit of a decentralized peripheral module. The buffer circuit has three input and three output signal storage areas, which can be selectively connected to a bus interface or a module interface via a selection circuit. Thus the process signal transfer from an intelligent unit arranged on the module to a unit of a higher level than the module and vice-versa can be completely separated.
IPC 1-7
IPC 8 full level
G05B 19/05 (2006.01); G05B 19/042 (2006.01)
CPC (source: EP KR US)
G05B 19/0423 (2013.01 - EP KR US); G05B 2219/21034 (2013.01 - KR); G05B 2219/21059 (2013.01 - KR); G05B 2219/25096 (2013.01 - KR)
Designated contracting state (EPC)
AT CH DE FR GB LI
DOCDB simple family (publication)
US 5927218 A 19990727; AT E186408 T1 19991115; CN 1191615 A 19980826; DE 19529718 A1 19970213; DE 19529718 C2 20000323; DE 59603583 D1 19991209; EP 0843843 A1 19980527; EP 0843843 B1 19991103; JP H11510930 A 19990921; KR 19990036276 A 19990525; WO 9707442 A1 19970227
DOCDB simple family (application)
US 1171098 A 19980624; AT 96928325 T 19960724; CN 96195827 A 19960724; DE 19529718 A 19950811; DE 59603583 T 19960724; DE 9601367 W 19960724; EP 96928325 A 19960724; JP 50880897 A 19960724; KR 19980700944 A 19980209