Global Patent Index - EP 0845181 A4

EP 0845181 A4 20010718 - LINK SCHEDULING

Title (en)

LINK SCHEDULING

Title (de)

VERBINDUNGSABLAUFFOLGEPLANUNG

Title (fr)

ORDONNANCEMENT DES LIAISONS

Publication

EP 0845181 A4 20010718 (EN)

Application

EP 96924603 A 19960718

Priority

  • US 9611919 W 19960718
  • US 149895 P 19950719

Abstract (en)

[origin: WO9704561A1] Methods and apparatus for scheduling cell transmission over a network link by a switch. The switch includes a plurality of queues associated with each link. Lists of queues are maintained for each link. In one embodiment, each link is associated with more than one type of list (with the list type corresponding to a scheduling category) (61) and more than one prioritized list of each type (with the priority of the list corresponding to a quality of service). The scheduling lists (61) are accessed to permit cell transmission from a queue (35, 28) contained therein in a predetermined sequence as a function of scheduling category, priority within a particular scheduling category and whether the bandwidth requirement for the particular scheduling category has been met. With this arrangement, maximum permissible delay requirements for each scheduling category are met.

IPC 1-7

H04L 12/56

IPC 8 full level

G06F 9/46 (2006.01); G06F 12/02 (2006.01); G06F 15/173 (2006.01); H04L 1/22 (2006.01); H04L 12/18 (2006.01); H04L 12/24 (2006.01); H04L 12/46 (2006.01); H04L 12/54 (2013.01); H04L 12/56 (2006.01); H04L 13/08 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01); H04M 3/00 (2006.01); H04M 3/08 (2006.01); H04M 3/22 (2006.01); H04Q 3/00 (2006.01); H04Q 3/545 (2006.01); H04Q 11/04 (2006.01); H04J 3/06 (2006.01); H04L 7/04 (2006.01)

CPC (source: EP)

G06F 15/17375 (2013.01); H04L 12/4608 (2013.01); H04L 12/5601 (2013.01); H04L 12/5602 (2013.01); H04L 47/10 (2013.01); H04L 47/11 (2013.01); H04L 47/18 (2013.01); H04L 47/26 (2013.01); H04L 47/266 (2013.01); H04L 47/29 (2013.01); H04L 47/30 (2013.01); H04L 47/621 (2013.01); H04L 49/106 (2013.01); H04L 49/107 (2013.01); H04L 49/153 (2013.01); H04L 49/1553 (2013.01); H04L 49/1576 (2013.01); H04L 49/203 (2013.01); H04L 49/253 (2013.01); H04L 49/255 (2013.01); H04L 49/256 (2013.01); H04L 49/3081 (2013.01); H04L 49/309 (2013.01); H04L 49/455 (2013.01); H04L 49/552 (2013.01); H04L 49/555 (2013.01); H04Q 11/0478 (2013.01); H04J 3/0682 (2013.01); H04J 3/0685 (2013.01); H04L 7/046 (2013.01); H04L 2012/5614 (2013.01); H04L 2012/5616 (2013.01); H04L 2012/5627 (2013.01); H04L 2012/5628 (2013.01); H04L 2012/5629 (2013.01); H04L 2012/5631 (2013.01); H04L 2012/5632 (2013.01); H04L 2012/5634 (2013.01); H04L 2012/5635 (2013.01); H04L 2012/5642 (2013.01); H04L 2012/5643 (2013.01); H04L 2012/5647 (2013.01); H04L 2012/5648 (2013.01); H04L 2012/5649 (2013.01); H04L 2012/5651 (2013.01); H04L 2012/5652 (2013.01); H04L 2012/5672 (2013.01); H04L 2012/5679 (2013.01); H04L 2012/5681 (2013.01); H04L 2012/5682 (2013.01); H04L 2012/5683 (2013.01); H04L 2012/5685 (2013.01)

Citation (search report)

  • [X] NOBORU ENDO: "SHARED BUFFER MEMORY SWITCH FOR AN ATM EXCHANGE", IEEE TRANSACTIONS ON COMMUNICATIONS,US,IEEE INC. NEW YORK, vol. 41, no. 1, 1993, pages 237 - 245, XP000367768, ISSN: 0090-6778
  • [X] CHAO H J ET AL: "ARCHITECTURE DESIGN OF A GENERALIZED PRIORITY QUEUE MANAGER FOR ATMSWITCHES", PROCEEDINGS OF THE INTERNATIONAL SWITCHING SYMPOSIUM,DE,BERLIN, VDE VERLAG, vol. SYMP. 15, 23 April 1995 (1995-04-23), pages 394 - 398, XP000495601, ISBN: 3-8007-2093-0
  • See references of WO 9704561A1

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

WO 9704561 A1 19970206; AU 6500996 A 19970218; EP 0845181 A1 19980603; EP 0845181 A4 20010718; JP 2000501897 A 20000215

DOCDB simple family (application)

US 9611919 W 19960718; AU 6500996 A 19960718; EP 96924603 A 19960718; JP 50606697 A 19960718