EP 0845810 B1 20030102 - Method of manufacturing of a large scale integrated circuit
Title (en)
Method of manufacturing of a large scale integrated circuit
Title (de)
Verfahren zur Herstellung einer hochintegrierten Schaltung
Title (fr)
Procédé de fabrication d'un circuit à grande échelle
Publication
Application
Priority
JP 31892896 A 19961129
Abstract (en)
[origin: EP0845810A1] The present invention relates to a method of manufacturing a large-scale-integration circuit device, comprising: the steps of generating (59) logic library data with respect to a macro comprising a macro core having a predetermined function and boundary cells positioned near input and output terminals thereof, the logic library data including delay characteristic data of the boundary cells given as attribute data to the input and output terminals; designing (51) a logic circuit having at least a plurality of cells and the macro, the cells being connected to the macro core through the boundary cells connected to the input and output terminals; calculating (52) a delay time of the macro based on the delay characteristic data with respect to the designed logic circuit; and effecting a logic simulation (57) on the designed logic circuit based on the calculated delay time. <IMAGE>
IPC 1-7
IPC 8 full level
G01R 31/28 (2006.01); G06F 17/50 (2006.01); H01L 21/82 (2006.01); H01L 27/02 (2006.01)
CPC (source: EP US)
G06F 30/33 (2020.01 - EP US); H01L 27/0207 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0845810 A1 19980603; EP 0845810 B1 20030102; DE 69718134 D1 20030206; DE 69718134 T2 20090917; JP 3938220 B2 20070627; JP H10162040 A 19980619; KR 100336826 B1 20021025; KR 19980042220 A 19980817; US 6012833 A 20000111
DOCDB simple family (application)
EP 97308443 A 19971023; DE 69718134 T 19971023; JP 31892896 A 19961129; KR 19970058873 A 19971108; US 87808097 A 19970618