EP 0908827 A2 19990414 - Memory interface device and memory address generation device
Title (en)
Memory interface device and memory address generation device
Title (de)
Speicherschnittstellenvorrichtung und Vorrichtung zur Speicheradressengeneration
Title (fr)
Dispositif d'interface de mémoire et dispositif de génération d'adresses de mémoire
Publication
Application
Priority
- JP 27175197 A 19971003
- JP 35852897 A 19971225
Abstract (en)
A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 13/16 (2006.01); H04N 7/26 (2006.01); H04N 7/50 (2006.01)
CPC (source: EP US)
G06F 9/345 (2013.01 - EP US); G06F 13/1673 (2013.01 - EP US); H04N 19/423 (2014.11 - EP US); H04N 19/61 (2014.11 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0908827 A2 19990414; EP 0908827 A3 20000503; EP 0908827 B1 20070103; EP 0908827 B8 20070509; DE 69836786 D1 20070215; DE 69836786 T2 20070426; EP 1691296 A2 20060816; EP 1691296 A3 20100317; US 2001056526 A1 20011227; US 2002184464 A1 20021205; US 6453394 B2 20020917; US 6732252 B2 20040504
DOCDB simple family (application)
EP 98118641 A 19981002; DE 69836786 T 19981002; EP 06011660 A 19981002; US 16578598 A 19981002; US 19597502 A 20020716