EP 0920024 A3 19990630 -
Publication
Application
Priority
JP 32882797 A 19971128
Abstract (en)
[origin: EP0920024A2] A semiconductor memory device includes a plurality of banks, a timing control circuit, and latch circuits. The timing control circuit is arranged commonly to the plurality of banks and outputs a signal for activating each bank and a signal for precharging each bank in a predetermined order at predetermined timings. Each latch circuit is arranged for each bank and latches the state of a signal output from the timing control circuit. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 11/41 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 11/401 (2006.01); G11C 11/407 (2006.01); G11C 11/409 (2006.01); G11C 11/4094 (2006.01)
CPC (source: EP KR US)
G11C 7/22 (2013.01 - EP US); G11C 8/18 (2013.01 - EP US); G11C 11/401 (2013.01 - KR); G11C 11/4094 (2013.01 - EP US)
Citation (search report)
- [A] US 5036493 A 19910730 - NIELSEN MICHAEL J K [US]
- [PA] WO 9825345 A1 19980611 - MICRON TECHNOLOGY INC [US]
- [PA] GB 2316208 A 19980218 - FUJITSU LTD [JP]
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
EP 0920024 A2 19990602; EP 0920024 A3 19990630; EP 0920024 B1 20041208; CN 1132188 C 20031224; CN 1222738 A 19990714; DE 69828021 D1 20050113; DE 69828021 T2 20051201; JP 3259764 B2 20020225; JP H11162161 A 19990618; KR 100304771 B1 20010924; KR 19990045665 A 19990625; TW 434879 B 20010516; US 6088292 A 20000711
DOCDB simple family (application)
EP 98250416 A 19981128; CN 98124964 A 19981125; DE 69828021 T 19981128; JP 32882797 A 19971128; KR 19980051390 A 19981127; TW 87119516 A 19981124; US 19905298 A 19981124