Global Patent Index - EP 0933807 A3

EP 0933807 A3 2000-01-26 - Method for manufacturing a power semiconductor device

Title (en)

Method for manufacturing a power semiconductor device

Title (de)

Verfahren zur Herstellung eines Leistungshalbleiterbauelementes

Title (fr)

Procédé de fabrication d'un dispositif semi-conducteur de puissance

Publication

EP 0933807 A3 (DE)

Application

EP 98124404 A

Priority

DE 19804192 A

Abstract (en)

[origin: EP0933807A2] The method involves one step of forming a structure with doped regions (2) on each surface of two substrates (1) of electrically conductive doped semiconductor material. In the second step the substrates are thinned from an opposing surface. In the third step these surfaces are permanently and electrically conductively connected together. The third step may be carried out using wafer bonding. The third step is preferably carried out at temperatures less than 350 deg. C. In the first step structures of one or more IGBTs or one or more GTO thyristors may be formed.

IPC 1-7 (main, further and additional classification)

H01L 21/331; H01L 21/332

IPC 8 full level (invention and additional information)

H01L 29/74 (2006.01); H01L 21/20 (2006.01); H01L 21/301 (2006.01); H01L 21/331 (2006.01); H01L 21/332 (2006.01); H01L 21/336 (2006.01); H01L 21/60 (2006.01); H01L 29/739 (2006.01); H01L 29/749 (2006.01); H01L 29/78 (2006.01)

CPC (invention and additional information)

H01L 24/80 (2013.01); H01L 21/2007 (2013.01); H01L 29/66333 (2013.01); H01L 29/66348 (2013.01); H01L 29/66363 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01023 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01)

Combination set (CPC)

  1. H01L 2924/1301 + H01L 2924/00
  2. H01L 2924/1305 + H01L 2924/00
  3. H01L 2924/12036 + H01L 2924/00

Citation (search report)

  • [DY] US 5608237 A 19970304 - AIZAWA YOSHIAKI [JP], et al
  • [XY] PATENT ABSTRACTS OF JAPAN vol. 13, no. 404 (E - 817) 7 September 1989 (1989-09-07)
  • [DY] T. OGURA ET LA.: "High frequency 6000 V double gate GTOs with buried gate structure", PROCEEDINGS OF 1990 INTERNATIONAL SYMPOSIUM ON POWER SWMICONDUCTOR DEVICES & ICS, 1990, tokyo, japan, pages 252 - 255, XP002123881

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

DOCDB simple family

EP 0933807 A2 19990804; EP 0933807 A3 20000126; EP 0933807 B1 20060614; DE 19804192 A1 19990812; DE 59813599 D1 20060727; JP 3848479 B2 20061122; JP H11340246 A 19991210; KR 100491211 B1 20050525; KR 19990072306 A 19990927; US 6066542 A 20000523