EP 0942434 B1 20040901 - Shift register and microprocessor arrangement
Title (en)
Shift register and microprocessor arrangement
Title (de)
Schieberegister und Mikroprozessoranordnung
Title (fr)
Registre à décalage et dispositif à microprocesseurs
Publication
Application
Priority
DE 19811201 A 19980309
Abstract (en)
[origin: EP0942434A1] Shift register (1) has data input (D) for acquisition of data bits, binary storage elements (4-6) for the acquired data bits, data output (Q) for stored data bits and a first control input for a binary control signal. Control logic (7) drives the storage elements to accept a new data bit via the data input and/or to output one of the stored data bits via the data output for a predefined value of the first control signal. Second control logic circuit (10) increases the stored level value by one for a certain value of the first control signal. An independent claim is also included for a microprocessor arrangement.
IPC 1-7
IPC 8 full level
G06F 9/46 (2006.01); G11C 19/00 (2006.01)
CPC (source: EP)
G11C 19/00 (2013.01)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0942434 A1 19990915; EP 0942434 B1 20040901; DE 19811201 A1 19990916; DE 59910369 D1 20041007
DOCDB simple family (application)
EP 99250069 A 19990308; DE 19811201 A 19980309; DE 59910369 T 19990308