EP 0956592 A1 19991117 - HIGHLY-INTEGRATED SEMICONDUCTOR MEMORY AND PROCESS FOR PREPARATION OF THE MEMORY
Title (en)
HIGHLY-INTEGRATED SEMICONDUCTOR MEMORY AND PROCESS FOR PREPARATION OF THE MEMORY
Title (de)
HOCHINTEGRIERTER HALBLEITERSPEICHER UND VERFAHREN ZUR HERSTELLUNG DES HALBLEITERSPEICHERS
Title (fr)
MEMOIRE A SEMI-CONDUCTEUR HAUTEMENT INTEGREE ET PROCEDE DE FABRICATION DE CETTE MEMOIRE
Publication
Application
Priority
- DE 9602386 W 19961211
- DE 19600307 A 19960105
Abstract (en)
[origin: WO9725744A1] The invention concerns a highly-integrated semiconductor memory with an EPROM cell in the form of a column with a floating gate and a control gate and a process for the preparation of the same. The EPROM cell is so thinly built that it is completely depleted. The control gate of the preferred split gate flash EPROM cell or the dual gate flash EPROM cell consists of p<+-> dosed semiconductor material so that a very good difference threshold ratio can be expected from the fully depleted cylinder.
IPC 1-7
IPC 8 full level
H10B 69/00 (2023.01); H01L 21/8247 (2006.01); H01L 29/00 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 41/27 (2023.01); G11C 16/02 (2006.01)
CPC (source: EP KR US)
H10B 41/27 (2023.02 - EP US); H10B 69/00 (2023.02 - EP KR US)
Designated contracting state (EPC)
AT CH DE ES FR GB IT LI
DOCDB simple family (publication)
WO 9725744 A1 19970717; CN 1207204 A 19990203; CN 1286182 C 20061122; DE 19600307 C1 19980108; EP 0956592 A1 19991117; IN 190928 B 20030906; JP 3246917 B2 20020115; JP H11502066 A 19990216; KR 100417449 B1 20040604; KR 19990076991 A 19991025; RU 2153210 C2 20000720; UA 46079 C2 20020515; US 6157060 A 20001205
DOCDB simple family (application)
DE 9602386 W 19961211; CN 96199545 A 19961211; DE 19600307 A 19960105; EP 96946072 A 19961211; IN 5CA1997 A 19970101; JP 52472197 A 19961211; KR 19980705121 A 19980703; RU 98114501 A 19961211; UA 98073472 A 19961211; US 11112098 A 19980706