Global patent index - EP 0969289 A1

EP 0969289 A1 2000-01-05 - TESTING THE FUNCTIONAL BLOCKS IN A SEMICONDUCTOR INTEGRATED CIRCUIT

Title (en)

TESTING THE FUNCTIONAL BLOCKS IN A SEMICONDUCTOR INTEGRATED CIRCUIT

Title (de)

PRÜFEN DER FUNKTIONELLEN BLÖCKE IN EINER INTEGRIERTEN HALBLEITERSCHALTUNG

Title (fr)

TEST DES BLOCS FONCTIONNELS DANS UN CIRCUIT INTEGRE A SEMI-CONDUCTEUR

Publication

EP 0969289 A1 (EN)

Application

EP 98909824 A

Priority

  • JP 9801249 W
  • JP 6766797 A

Abstract (en)

A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5). <IMAGE>

IPC 1-7 (main, further and additional classification)

G01R 31/3185; G01R 31/3187; H01L 21/822; H01L 27/04

IPC 8 full level (invention and additional information)

H01L 27/02 (2006.01); G06F 11/22 (2006.01)

CPC (invention and additional information)

H01L 27/0207 (2013.01); G06F 11/2273 (2013.01)

Citation (search report)

  • [X] US 5258985 A
  • [X] EP 0472818 A2
  • [X] CHIN TSUNG MO ET AL: "A self-diagnostic BIST memory design scheme" MEMORY TECHNOLOGY, DESIGN AND TESTING, 1994., RECORDS OF THE IEEE INTERNATIONAL WORKSHOP ON SAN JOSE, CA, USA 8-9 AUG. 1994, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, 8 August 1994 (1994-08-08), pages 7-9, XP010136852 ISBN: 0-8186-6245-X
  • [X] WUNDERLICH H-J ET AL: "Bit-flipping BIST" COMPUTER-AIDED DESIGN, 1996. ICCAD-96. DIGEST OF TECHNICAL PAPERS., 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON SAN JOSE, CA, USA 10-14 NOV. 1996, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 10 November 1996 (1996-11-10), pages 337-343, XP010205403 ISBN: 0-8186-7597-7
  • See also references of WO 9843101A1

Designated contracting state (EPC)

DE FR GB

EPO simple patent family

EP 0969289 A1 20000105; EP 0969289 A4 20040908; EP 0969289 B1 20061213; DE 69836625 D1 20070125; US 2004139376 A1 20040715; US 6708301 B1 20040316; WO 9843101 A1 19981001

INPADOC legal status

2010-04-30 [PG25 FR] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

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2007-11-21 [26N] NO OPPOSITION FILED

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2007-06-01 [ET] FR: TRANSLATION FILED

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2007-01-25 [REF] CORRESPONDS TO:

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2006-12-13 [AK] DESIGNATED CONTRACTING STATES:

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2006-12-06 [RTI1] TITLE (CORRECTION)

- Free Format Text: TESTING THE FUNCTIONAL BLOCKS IN A SEMICONDUCTOR INTEGRATED CIRCUIT

2006-06-14 [RTI1] TITLE (CORRECTION)

- Free Format Text: TESTING THE FUNCTIONAL BLOCKS IN A SEMICONDUCTOR INTEGRATED CIRCUIT

2004-11-17 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20041004

2004-09-08 [A4] SUPPLEMENTARY SEARCH REPORT

- Effective date: 20040723

2004-09-08 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: 7G 01R 31/3185 A

2004-09-08 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: 7G 01R 31/3187 B

2004-09-08 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: 7H 01L 21/822 B

2004-09-08 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: 7H 01L 27/04 B

2000-01-05 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 19991020

2000-01-05 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

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