Global Patent Index - EP 0978177 A1

EP 0978177 A1 20000209 - PROGRAMMABLE PHASE ADJUSTMENT

Title (en)

PROGRAMMABLE PHASE ADJUSTMENT

Title (de)

PROGRAMMIERBARE PHASENANPASSUNG

Title (fr)

DISPOSITIF D'ADAPTATION DE PHASE PROGRAMMABLE

Publication

EP 0978177 A1 (DE)

Application

EP 98931988 A

Priority

  • DE 9801138 W
  • DE 19717585 A

Abstract (en)

[origin: WO9849802A1] According to the invention, a delay signal from the detected phase status is detected in a phase adjustment circuit used to generate a systemic clock signal in relation to an incoming data signal from a locally existing clock signal, wherein a memory which is addressed by the detected phase status produces an allocated delay signal. In a special embodiment, the memory is allocated an address whose last detected delay is compensated. In another embodiment, a control with a memory is common to circuits for several data signals. The phase adjustment, which automatically recognizes a loop that is better suited for timing than the loop that is momentarily used, can be fully integrated and avoids areas of the circuit which are operated with a higher bit rate than that of the clock signal.

IPC 1-7

H04L 7/033; H03L 7/081

IPC 8 full level

H03L 7/081 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01)

CPC (source: EP)

H03L 7/0814 (2013.01); H04L 7/0338 (2013.01); H04L 7/0083 (2013.01)

Citation (search report)

See references of WO 9849802A1

Designated contracting state (EPC)

AT CH DE FI FR GB IT LI SE

DOCDB simple family (publication)

WO 9849802 A1 19981105; EP 0978177 A1 20000209; US 6603829 B1 20030805

DOCDB simple family (application)

DE 9801138 W 19980423; EP 98931988 A 19980423; US 40351399 A 19991022