Global Patent Index - EP 0980040 B1

EP 0980040 B1 2003-06-11 - Pseudo lockstep data processing system

Title (en)

Pseudo lockstep data processing system

Title (de)


Title (fr)

Système de traitement de données pseudo lockstep


EP 0980040 B1 (EN)


EP 99306330 A


GB 9817598 A

Abstract (en)

[origin: EP0980040A2] A data processing system comprising a common memory shared by a first and second data processor circuit, in which each processor circuit executes the same sequence of operational steps and each is connected to the common memory. An isolating device connected between the first data processor circuit and the common memory restricts access by the first processor circuit to the common memory, to read-only access. The first data processor circuit is arranged to execute each operational step a set time period later than the second data processor circuit. A comparator compares the output signals of the two processor circuits in order to detect faulty operation but, before the comparison, the outputs of the second processor circuit are delayed by the set time period. <IMAGE>

IPC 1-7 (main, further and additional classification)

G06F 11/16

IPC 8 full level (invention and additional information)

G06F 9/00 (2006.01); G06F 11/16 (2006.01)

CPC (invention and additional information)

G06F 11/1695 (2013.01); G06F 11/1679 (2013.01)

Citation (examination)

US 5231640 A 19930727 - HANSON DAVID G [US], et al

Designated contracting state (EPC)


DOCDB simple family

EP 0980040 A2 20000216; EP 0980040 A3 20000809; EP 0980040 B1 20030611; CN 1154944 C 20040623; CN 1248748 A 20000329; DE 69908717 D1 20030717; DE 69908717 T2 20031211; ES 2199527 T3 20040216; GB 2340627 A 20000223; GB 2340627 B 20001004; GB 9817598 D0 19981007; HK 1024067 A1 20050401; RU 99118019 A 20010827; US 6519710 B1 20030211