EP 0980555 A1 20000223 - METHOD AND APPARATUS FOR COMPILING ONE CIRCUIT IN A SEQUENCE OF CIRCUITS WITHIN A PROGRAMMABLE GATE ARRAY
Title (en)
METHOD AND APPARATUS FOR COMPILING ONE CIRCUIT IN A SEQUENCE OF CIRCUITS WITHIN A PROGRAMMABLE GATE ARRAY
Title (de)
VERFAHREN UND GERÄT ZUR KOMPILIERUNG EINER SCHALTUNG IN EINER SEQUENZVON SCHALTUNGEN IN EINEM PRGRAMMIERBAREN GATTERFIELD
Title (fr)
PROCEDE ET DISPOSITIF PERMETTANT DE COMPILER UN CIRCUIT DANS UNE SEQUENCE DE CIRCUITS A L'INTERIEUR D'UN RESEAU PREDIFFUSE PROGRAMMABLE
Publication
Application
Priority
- US 9711628 W 19970610
- US 1810396 P 19960610
Abstract (en)
[origin: WO9748062A1] A programmable gate array (70) including a plurality of logic gates can be programmed to constitute a series of configurations chosen to consist of a series of circuits. The series of circuits are chosen to accomplish a desired communication capability. Depending upon the circumstances of operation, the series of circuits can initially consist of a grouping of communications initialization circuits, then later a grouping of communications maintenance circuits, and still later a grouping of communications termination circuits.
IPC 1-7
IPC 8 full level
G06F 17/50 (2006.01); H03K 19/177 (2006.01)
CPC (source: EP)
G06F 30/34 (2020.01)
Citation (search report)
See references of WO 9748062A1
Designated contracting state (EPC)
AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
WO 9748062 A1 19971218; AU 3794197 A 19980107; CA 2257996 A1 19971218; EP 0980555 A1 20000223; JP 2000512461 A 20000919; JP 4446492 B2 20100407; KR 20000016513 A 20000325
DOCDB simple family (application)
US 9711628 W 19970610; AU 3794197 A 19970610; CA 2257996 A 19970610; EP 97934879 A 19970610; JP 50190598 A 19970610; KR 19980710099 A 19981210