Global Patent Index - EP 0986787 A2

EP 0986787 A2 2000-03-22 - PROCESSOR INTERFACING TO MEMORY MAPPED COMPUTING ENGINE

Title (en)

PROCESSOR INTERFACING TO MEMORY MAPPED COMPUTING ENGINE

Title (de)

PROZESSOR, DER MIT EINER SPEICHERABBILDENDEN RECHENMACHINE EINE SCHNITTSTELLE BILDET

Title (fr)

PROCESSEUR ASSURANT L'INTERFACE A UN MOTEUR DE CALCUL MEMO-CENTRIQUE

Publication

EP 0986787 A2 (EN)

Application

EP 98924857 A

Priority

  • US 9810549 W
  • US 86914897 A
  • US 86927797 A

Abstract (en)

[origin: WO9855932A2] A memory subsystem that is partitioned into two or more blocks of memory space in which one block of the memory communicates with an I/O or DMA channel to load data, while the other block of memory simultaneously communicates with one or more execution units that carry out arithmetic operations on data in the second block. Results are written back to the second block of memory. Upon conclusion of that process, the memory blocks are effectively "swapped" so that the second block, now holding processed (output) data, communicates with the I/O channel to output that data, while the execution unit communicates with the first block, which by then has been filled with new input data. Methods and apparatus are shown for implementing this memory swapping technique in real time so that the execution unit is never idle. A method of interfacing a processor bus to a computation engine having a microprogrammable memory-centric controller and an array of memory, comprising the steps of providing a predetermined series of microcode instructions for execution by the MCC; selecting a start address within the series of microcode instructions for carrying out a corresponding operation; and executing the series of microcode instructions in the MCC beginning at the selected start address so as to carry out the corresponding operation in the engine. The present invention is useful in a wide variety of signal processing applications including programmable MPEG encode and decode, graphics, speech processing, image processing, array processors, etc. In telecommunications, the invention can be used, for example, for switching applications in which multiple I/O channels are operated simultaneously.

IPC 1-7 (main, further and additional classification)

G06F 13/00

IPC 8 full level (invention and additional information)

G06F 9/38 (2006.01); H04N 7/26 (2006.01); H04N 7/50 (2006.01)

CPC (invention and additional information)

G06F 9/3897 (2013.01); G06F 9/3879 (2013.01); H04N 19/423 (2014.11); H04N 19/61 (2014.11)

Citation (search report)

See references of WO 9855932A3

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 9855932 A2 19981210; WO 9855932 A3 19990812; AU 7693198 A 19981221; EP 0986787 A2 20000322

INPADOC legal status


2001-02-07 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20000106

2000-03-22 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 19990108

2000-03-22 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A2

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE