Global Patent Index - EP 0989565 A1

EP 0989565 A1 2000-03-29 - Integrated memory device

Title (en)

Integrated memory device

Title (de)

Integrierter Speicher

Title (fr)

Dispositif de mémoire intégrée

Publication

EP 0989565 A1 (DE)

Application

EP 99118399 A

Priority

DE 19842852 A

Abstract (en)

An integrated memory/store includes storage or memory cells for storage of information and which are arranged in a matrix of cells at the crossing points of the bit-lines (BL) and the word lines (WL). A word-line decoder (WLDEC) is used to address the word-lines, and at least one evaluating unit (SA) is provided for assessing the information read from the memory cells (MC) on to the bit-lines (BL), and is provided with an activating input. A logic unit (OR) carries out an OR-function with the inputs which are connected to the end of each word-line facing away from the word-line decoder (WLDEC), and has an output which is connected to the activating input of the evaluating unit (SA).

Abstract (de)

Der integrierte Speicher weist Speicherzellen (MC) zum Speichern von Informationen auf, die in einem Zellenfeld in Kreuzungspunkten von Bitleitungen (BL) und Wortleitungen (WL) angeordnet sind. Außerdem weist er einen Wortleitungsdecoder (WLDEC) auf, über den die Wortleitungen (WL) adressierbar sind, und wenigstens eine Bewertereinheit (SA) zum Bewerten von aus den Speicherzellen (MC) auf die Bitleitungen (BL) ausgelesenen Informationen, die einen Aktivierungseingang aufweist. Außerdem weist der integrierte Speicher eine Logikeinheit (OR) auf zur Ausführung einer Oder-Funktion mit Eingängen, die mit dem vom Wortleitungsdecoder (WLDEC) abgewandten Ende je einer der Wortleitungen (WL) verbunden sind, und mit einem Ausgang, der mit dem Aktivierungseingang der Bewertereinheit (SA) verbunden ist. Die Logikeinheit (OR) dient zu einer zeitoptimierten Aktivierung der Bewertereinheit (SA), sobald eine der Wortleitungen (WL) vom Wortleitungsdecoder (WLDEC) ausgewählt worden ist. <IMAGE>

IPC 1-7 (main, further and additional classification)

G11C 7/06; G11C 11/409; H01L 27/105; H01L 27/108

IPC 8 full level (invention and additional information)

G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 8/08 (2006.01); G11C 8/18 (2006.01); G11C 11/4091 (2006.01)

CPC (invention and additional information)

G11C 7/06 (2013.01); G11C 8/08 (2013.01); G11C 8/18 (2013.01); G11C 11/4091 (2013.01)

Citation (search report)

Designated contracting state (EPC)

DE FR GB IE IT

EPO simple patent family

DE 19842852 A1 20000323; DE 19842852 B4 20050519; EP 0989565 A1 20000329; EP 0989565 B1 20020821; TW 442792 B 20010623; US 6181624 B1 20010130

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