Global Patent Index - EP 0991075 A1

EP 0991075 A1 2000-04-05 - Circuit device for providing a hierarchical row decoding in semiconductor memory devices

Title (en)

Circuit device for providing a hierarchical row decoding in semiconductor memory devices

Title (de)

Schaltungsanordnung zur hierarchischen Zellendekodierung einer Halbleiterspeicheranordnung

Publication

EP 0991075 A1 (EN)

Application

EP 98830570 A

Priority

EP 98830570 A

Abstract (en)

The invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and comprising at least one matrix of memory cells (5) with sectors (3,4) organized into columns, wherein each sector has a specific group of local word lines (LWL) individually connected to a main word line (MWL) running through all of the matrix sectors which have rows in common. The device comprises a first transistor (M1) of the PMOS type having its conduction terminals connected, the one to the main word line (MWL) and the other to the local word line (LWL), and a second transistor (M3) of the NMOS type having its conduction terminals connected, the one to the local word line (LWL) and the other to a reference voltage (GND). <IMAGE>

IPC 1-7 (main, further and additional classification)

G11C 8/00

IPC 8 full level (invention and additional information)

G11C 16/06 (2006.01); G11C 8/14 (2006.01); G11C 16/04 (2006.01)

CPC (invention and additional information)

G11C 16/0416 (2013.01); G11C 8/14 (2013.01)

Citation (search report)

  • [XY] US 5506816 A 19960409 - HIROSE RYAN T [US], et al
  • [Y] EP 0822660 A1 19980204 - SGS THOMSON MICROELECTRONICS [IT]
  • [A] DE 4117881 A1 19911212 - MITSUBISHI ELECTRIC CORP [JP]
  • [A] TAKESHIMA T ET AL: "A 3.3V SINGLE-POWER-SUPPLY 64MB FLASH MEMORY WITH DYNAMIC BIT-LINE LATCH (DBL) PROGRAMMING SCHEME", IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, vol. 37, 1 February 1994 (1994-02-01), pages 148/149, 327, XP000507095

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

EP 0991075 A1 20000405; EP 0991075 B1 20040506; DE 69823659 D1 20040609; JP 2000113689 A 20000421; JP 4316743 B2 20090819; US 2002021584 A1 20020221; US 6515911 B2 20030204

INPADOC legal status


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