Global patent index - EP 1018149 A1

EP 1018149 A1 2000-07-12 - METHOD AND APPARATUS FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT INTERCONNECT FABRICATION

Title (en)

METHOD AND APPARATUS FOR HIGH-PERFORMANCE INTEGRATED CIRCUIT INTERCONNECT FABRICATION

Title (de)

METHODE UND APPARAT ZUR HOCHLEISTUNGS-IC-VERDRAHTUNGS-HERSTELLUNG

Title (fr)

PROCEDE ET DISPOSITIF POUR LA REALISATION D'INTERCONNEXIONS SUR CIRCUIT INTEGRE HAUTE PERFORMANCE

Publication

EP 1018149 A1 (EN)

Application

EP 98947076 A

Priority

  • US 9819367 W
  • US 93342097 A

Abstract (en)

[origin: WO9914800A1] A method and apparatus for multi-level interconnection fabrication on an integrated circuit are disclosed. A liner/barrier layer (172) and a conductive layer (174) are deposited to fill the trenches and holes in an insulating layer. A globally planarized disposable layer (176) is then formed on the conductive layer (174). The layers are removed at substantially similar rates of material removal, and the removal is stopped when both layers have been removed except for material from the conductive layer filling the trenches and holes. In one implementation, the conductive layer (174) is a copper layer and the globally planarized disposable layer (176) is a tin or tin alloy layer and its formation includes deposition, melting, and resolidification. Further, the removal can be accomplished by an ion-beam etch which is stopped based on in-situ real-time measurement of the wafer surface reflectance. The method employs a cluster tool apparatus.

IPC 1-7 (main, further and additional classification)

H01L 21/283; C23C 16/00; H01L 21/302

IPC 8 full level (invention and additional information)

H01L 21/302 (2006.01); H01L 21/3205 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01)

CPC (invention and additional information)

H01L 21/7684 (2013.01); H01L 21/32115 (2013.01); H01L 21/32131 (2013.01)

Citation (search report)

See references of WO 9914800A1

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 9914800 A1 19990325; EP 1018149 A1 20000712; JP 2001516970 A 20011002; TW 426983 B 20010321

INPADOC legal status

2001-04-11 [18W] WITHDRAWN

- Ref Legal Event Code: 18W

- Date of withdrawal: 20010216

2000-07-12 [17P] REQUEST FOR EXAMINATION FILED

- Ref Legal Event Code: 17P

- Effective date: 20000413

2000-07-12 [AK] DESIGNATED CONTRACTING STATES:

- Ref Legal Event Code: AK

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE