Global Patent Index - EP 1023681 A4

EP 1023681 A4 2000-10-25 - SYSTEM FOR LOGIC EXTRACTION FROM A LAYOUT DATABASE

Title (en)

SYSTEM FOR LOGIC EXTRACTION FROM A LAYOUT DATABASE

Title (de)

SYSTEM ZUR LOGISCHEN EXTRAKTION AUS EINER DATENBANK-ANORDNUNG

Title (fr)

SYSTEME POUR L'EXTRACTION DE STRUCTURE LOGIQUE D'UNE BASE DE DONNEES D'IMPLANTATION

Publication

EP 1023681 A4 (EN)

Application

EP 97912778 A

Priority

US 9718844 W

Abstract (en)

[origin: WO9919818A1] A system and process for logic extraction (15) from the layout of logic blocks (14) is described. Logic design information (15) is extracted from a transistor level net list which is stored in a memory (14). The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The logic extraction process (15) comprises processing the transistor level net list in the memory to define groups of transistors according to whether there is a connection or not to a supply voltage, to a reference voltage, and according to the transistor type (201). The groups of transistors are analyzed according to their interconnections, and their membership in the groups (202). Finally, logic units are identified in response to the step of analyzing groups of transistors (203).

IPC 1-7 (main, further and additional classification)

G06F 17/50

IPC 8 full level (invention and additional information)

G06F 17/50 (2006.01); H01L 21/82 (2006.01)

CPC (invention and additional information)

G06F 17/5045 (2013.01)

Citation (search report)

  • [A] US 5629858 A 19970513 - KUNDU SANDIP [US], et al
  • [A] CHEN J -E ET AL: "My-box representation for faulty CMOS circuits", IEE PROCEEDINGS G (CIRCUITS, DEVICES AND SYSTEMS), JUNE 1990, UK, vol. 137, no. 3, pages 225 - 232, XP002145774, ISSN: 0956-3768
  • [A] MEYER W ET AL: "Fast, accurate, integrated gate and switch-level fault simulation", PROCEEDINGS OF ETC 93. THIRD EUROPEAN TEST CONFERENCE (CAT. NO.93TH0494-5), ROTTERDAM, NETHERLANDS, 19-22 APRIL 1993, 1993, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, pages 194 - 199, XP002145775, ISBN: 0-8186-3360-3
  • See also references of WO 9919818A1

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

WO 9919818 A1 19990422; EP 1023681 A1 20000802; EP 1023681 A4 20001025; JP 2001520420 A 20011030

INPADOC legal status


2016-10-19 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20160503

2003-12-03 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20031017

2001-01-31 [RAP1] TRANSFER OF RIGHTS OF AN EP PUBLISHED APPLICATION

- Owner name: MACRONIX INTERNATIONAL CO., LTD.

2000-10-25 [A4] DESPATCH OF SUPPLEMENTARY SEARCH REPORT

- Effective date: 20000912

2000-10-25 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A4

- Designated State(s): DE FR GB IT

2000-08-02 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20000403

2000-08-02 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): DE FR GB IT