Global Patent Index - EP 1025591 A1

EP 1025591 A1 2000-08-09 - VERTICAL MOS TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF

Title (en)

VERTICAL MOS TRANSISTOR AND METHOD FOR THE PRODUCTION THEREOF

Title (de)

VERTIKALER MOS-TRANSISTOR UND VERFAHREN ZU DESSEN HERSTELLUNG

Title (fr)

TRANSISTOR MOS VERTICAL ET SON PROCEDE DE PRODUCTION

Publication

EP 1025591 A1 (DE)

Application

EP 98955366 A

Priority

  • DE 9802946 W
  • DE 19746900 A

Abstract (en)

[origin: DE19746900A1] A first part (S/D1a) of a first source/drain area (S/D1) is arranged on at least one edge of a semiconductor structure (St) and at least one edge area of a surface (OH) of a semiconductor (St) bordering thereon. The dimension of the first part (S/D1a) of the first source/drain area (S/D1) perpendicular to the edge is smaller than an analogous dimension of the semiconductor structure (St) and smaller than the minimum structural dimension which can be produced according to current technology. In order to produce the inventive transistor, the mask used to make the semiconductor structure can be reduced in size to enable implantation of the first part (S/D1a) of the first source/drain area. In order to facilitate production of the first source/drain area (SD1) contact (K1), a second part (S/D1b) of the first source /drain area (S/D1) can be arranged inside an inner area of the surface (OH) of the seminconductor structure (St). The dimension of the second part (S/D1b) of the first source/drain area (S/D1) perpendicular to the surface (OH) of the semiconductor structure (St) is smaller than the analogous dimension of the first part (S/D1a) of the first source/drain area (S/D1).

IPC 1-7 (main, further and additional classification)

H01L 29/78; H01L 21/336; H01L 29/423

IPC 8 full level (invention and additional information)

H01L 29/41 (2006.01); H01L 21/336 (2006.01); H01L 29/78 (2006.01)

CPC (invention and additional information)

H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)

Citation (search report)

See references of WO 9922408A1

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

DE 19746900 A1 19990506; DE 19746900 C2 20020214; EP 1025591 A1 20000809; JP 2001521297 A 20011106; US 2001024858 A1 20010927; WO 9922408 A1 19990506

INPADOC legal status


2002-07-24 [18W] WITHDRAWN

- Date of withdrawal: 20020527

2000-08-09 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20000419

2000-08-09 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): DE FR GB IT