Global Patent Index - EP 1029360 A2

EP 1029360 A2 2000-08-23 - VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Title (en)

VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION

Title (de)

VERTIKALES ZWISCHENVERBINDUNGSVERFAHREN FÜR SILIZIUMSEGMENTE MIT DIELEKTRISCHER ISOLIERUNG

Title (fr)

PROCEDE D'INTERCONNEXION VERTICALE POUR SEGMENTS EN SILICIUM AVEC ISOLATION DIELECTRIQUE

Publication

EP 1029360 A2 (EN)

Application

EP 98944438 A

Priority

  • US 9816900 W
  • US 91562097 A
  • US 92027397 A

Abstract (en)

[origin: WO9909599A2] An apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A dielectric coating is applied to the die to provide a conformal coating to protect and insulate the die and a laser is used to ablate the area over the bond pads to remove the dielectric coating in order to provide for electrical connections to bond pads.

IPC 1-7 (main, further and additional classification)

H01L 29/43; H01L 23/485

IPC 8 full level (invention and additional information)

H01L 29/41 (2006.01); H01L 21/98 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01)

CPC (invention and additional information)

H01L 25/50 (2013.01); H01L 24/24 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/2919 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06593 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01032 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01075 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/14 (2013.01)

Combination set (CPC)

  1. H01L 2224/2919 + H01L 2924/0665 + H01L 2924/00
  2. H01L 2924/3512 + H01L 2924/00
  3. H01L 2924/14 + H01L 2924/00

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 9909599 A2 19990225; WO 9909599 A3 19990415; AU 9197698 A 19990308; EP 1029360 A2 20000823; EP 1029360 A4 20060412; JP 2001516148 A 20010925; KR 100593567 B1 20060628

INPADOC legal status


2010-08-25 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20100302

2006-09-06 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20060808

2006-04-12 [A4] SUPPLEMENTARY SEARCH REPORT

- Effective date: 20060223

2002-07-17 [RAP1] TRANSFER OF RIGHTS OF AN EP PUBLISHED APPLICATION

- Owner name: VERTICAL CIRCUITS, INC.

2002-06-05 [RAP1] TRANSFER OF RIGHTS OF AN EP PUBLISHED APPLICATION

- Owner name: VERTICAL CIRCUITS, INC.

2000-08-23 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20000320

2000-08-23 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A2

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE