Global Patent Index - EP 1031995 A1

EP 1031995 A1 2000-08-30 - Built-in self-test circuit for memory

Title (en)

Built-in self-test circuit for memory

Title (de)

Speicherschaltung mit eingebautem Selbsttest

Title (fr)

Circuit de mémoire à auto-test incorporé

Publication

EP 1031995 A1 (EN)

Application

EP 99103479 A

Priority

EP 99103479 A

Abstract (en)

A built-in self-test (BIST) circuit and a method for testing a memory device, especially applicable in a DRAM requiring a complex test algorithm. Two finite machines are used instead of a single finite state machine used in the conventional circuit. Therefore, the pipeline technique can be applied to divide the test pattern generation process into stages, leading to a higher-speed design. In addition, a technique of protocol based relaxation is also presented. By imposing a certain protocol on the two communicating finite machines, the timing criticality is further relaxed. Synthesis results show that the proposed BIST circuit can operate at the speed of as high as 450MHz using 0.25 mu m CMOS technology. <IMAGE>

IPC 1-7 (main, further and additional classification)

G11C 29/00; G01R 31/3181

IPC 8 full level (invention and additional information)

G01R 31/3181 (2006.01); G11C 29/36 (2006.01)

CPC (invention and additional information)

G11C 29/36 (2013.01); G01R 31/31813 (2013.01)

Citation (search report)

Designated contracting state (EPC)

DE FR GB NL

EPO simple patent family

EP 1031995 A1 20000830; EP 1031995 B1 20020522; DE 69901534 D1 20020627; DE 69901534 T2 20030109

INPADOC legal status


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2002-10-25 [ET] FR: TRANSLATION FILED

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- Document: DE 69901534 20020627

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