EP 1040483 A1 20001004 - MEMORY ADDRESSING
Title (en)
MEMORY ADDRESSING
Title (de)
SPEICHERADDRESSIERUNG
Title (fr)
ADRESSAGE DE MEMOIRE
Publication
Application
Priority
- IE 9800104 W 19981215
- IE 970886 A 19971215
- IE S980710 A 19980831
Abstract (en)
[origin: WO9931665A1] An ASIC circuit device microprocessor interface (10) has a UPI (17) which interfaces between external ports (18-21) and internal access registers (11). The access registers are connected to a RAM port controller (12(c)) and an internal register access controller (12(a)). These controllers interface between the access register (11) and the relevant memory or registers. Reads and writes are performed by an external processor (2) using the access registers (11).
IPC 1-7
IPC 8 full level
G11C 5/06 (2006.01); G11C 7/00 (2006.01); G11C 8/00 (2006.01)
CPC (source: EP)
G11C 5/066 (2013.01); G11C 7/00 (2013.01); G11C 8/00 (2013.01)
Citation (search report)
See references of WO 9931665A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
WO 9931665 A1 19990624; AU 1680299 A 19990705; EP 1040483 A1 20001004; IE S80916 B2 19990630; IE S980710 A2 19990630
DOCDB simple family (application)
IE 9800104 W 19981215; AU 1680299 A 19981215; EP 98961334 A 19981215; IE S980710 A 19980831