Global Patent Index - EP 1040483 A1

EP 1040483 A1 2000-10-04 - MEMORY ADDRESSING

Title (en)

MEMORY ADDRESSING

Title (de)

SPEICHERADDRESSIERUNG

Title (fr)

ADRESSAGE DE MEMOIRE

Publication

EP 1040483 A1 (EN)

Application

EP 98961334 A

Priority

  • IE 9800104 W
  • IE 970886 A
  • IE S980710 A

Abstract (en)

[origin: WO9931665A1] An ASIC circuit device microprocessor interface (10) has a UPI (17) which interfaces between external ports (18-21) and internal access registers (11). The access registers are connected to a RAM port controller (12(c)) and an internal register access controller (12(a)). These controllers interface between the access register (11) and the relevant memory or registers. Reads and writes are performed by an external processor (2) using the access registers (11).

IPC 1-7 (main, further and additional classification)

G11C 7/00; G11C 5/06; G11C 8/00

IPC 8 full level (invention and additional information)

G11C 5/06 (2006.01); G11C 7/00 (2006.01); G11C 8/00 (2006.01)

CPC (invention and additional information)

G11C 5/066 (2013.01); G11C 7/00 (2013.01); G11C 8/00 (2013.01)

Citation (search report)

See references of WO 9931665A1

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 9931665 A1 19990624; AU 1680299 A 19990705; EP 1040483 A1 20001004; IE S80916 B2 19990630; IE S980710 A2 19990630

INPADOC legal status


2003-06-04 [18R] REFUSED

- Ref Legal Event Code: 18R

- Effective date: 20021128

2001-03-07 [17Q] FIRST EXAMINATION REPORT

- Ref Legal Event Code: 17Q

- Effective date: 20010119

2000-10-04 [17P] REQUEST FOR EXAMINATION FILED

- Ref Legal Event Code: 17P

- Effective date: 20000614

2000-10-04 [AK] DESIGNATED CONTRACTING STATES:

- Ref Legal Event Code: AK

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE