EP 1057215 A1 20001206 - METHOD FOR PRODUCING CMOS TRANSISTORS AND RELATED DEVICES
Title (en)
METHOD FOR PRODUCING CMOS TRANSISTORS AND RELATED DEVICES
Title (de)
HERSTELLUNGSVERFAHREN VON CMOS-TRANSISTOREN UND DERARTIGE BAUELEMENTE
Title (fr)
PROCEDE DE REALISATION DE TRANSISTORS CMOS ET DISPOSITIFS ASSOCIES
Publication
Application
Priority
- FR 9903151 W 19991215
- FR 9816028 A 19981218
Abstract (en)
[origin: FR2787634A1] Engraving process comprises etching an active layer or rendering zones of the layer inactive to leave active islands for making sources (12), channels (10) and drains of N-type and P-type transistors. The active islands are covered by an insulating layer (8) e.g. of silicium oxide, covered in turn by a conducting layer (9) of N+ doped polycrystalline silicium, tungsten, molybdenum or aluminum, etched with the transistor grids. The procedure can employ a substrate (4) or glass, plastic or quartz.
IPC 1-7
IPC 8 full level
G02F 1/1368 (2006.01); G09F 9/30 (2006.01); G09F 9/35 (2006.01); H01L 21/336 (2006.01); H01L 21/77 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/08 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC (source: EP KR US)
H01L 27/12 (2013.01 - KR); H01L 27/1214 (2013.01 - EP US); H01L 27/1288 (2013.01 - EP US)
Citation (search report)
See references of WO 0038229A1
Designated contracting state (EPC)
DE GB
DOCDB simple family (publication)
FR 2787634 A1 20000623; FR 2787634 B1 20030912; EP 1057215 A1 20001206; JP 2002533925 A 20021008; KR 100722728 B1 20070529; KR 20010041092 A 20010515; US 6627489 B1 20030930; WO 0038229 A1 20000629
DOCDB simple family (application)
FR 9816028 A 19981218; EP 99958336 A 19991215; FR 9903151 W 19991215; JP 2000590208 A 19991215; KR 20007009131 A 20000818; US 60135000 A 20000818