EP 1058230 A1 20001206 - Method of addressing a memory-effect display panel
Title (en)
Method of addressing a memory-effect display panel
Title (de)
Verfahren zur Speicher-Steuerung einer Anzeige
Title (fr)
Procédé d'adressage d'un panneau de visualisation à effet mémoire
Publication
Application
Priority
FR 9907093 A 19990604
Abstract (en)
The present invention relates to a method of addressing a memory-effect display panel comprising cells defined at the intersection of arrays of crossed electrodes, the cells having two states, one being the "written" state and the other the "erased" state, the method consisting, over a given cycle time, in applying a sustain signal to all the cells, the sustain signal producing a sustain discharge in the cells in the written state, and in applying an address signal, comprising a semi-selective signal and a selective signal, in succession to the electrodes of one array, the semi-selective signal being applied simultaneously to different electrodes for at least part of the cycle time of the selective signal. The invention applies to coplanar-type and matrix-type AC plasma display panels. <IMAGE>
IPC 1-7
IPC 8 full level
G09G 3/20 (2006.01); G09G 3/292 (2013.01); G09G 3/293 (2013.01)
CPC (source: EP)
G09G 3/2927 (2013.01); G09G 3/293 (2013.01); G09G 2310/066 (2013.01)
Citation (search report)
- [A] FR 2769115 A1 19990402 - THOMSON TUBES ELECTRONIQUES [FR]
- [AD] FR 2744275 A1 19970801 - THOMSON CSF [FR]
- [A] EP 0680067 A2 19951102 - MATSUSHITA ELECTRONICS CORP [JP]
- [AD] EP 0135382 A1 19850327 - FUJITSU LTD [JP]
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 1058230 A1 20001206; FR 2795218 A1 20001222; FR 2795218 B1 20010817; JP 2001013922 A 20010119; TW 563083 B 20031121
DOCDB simple family (application)
EP 00401517 A 20000530; FR 9907093 A 19990604; JP 2000166381 A 20000602; TW 89110761 A 20000602