Global Patent Index - EP 1064682 A1

EP 1064682 A1 2001-01-03 - DRAM-CELL ARRANGEMENT AND METHOD OF PRODUCTION THEREOF

Title (en)

DRAM-CELL ARRANGEMENT AND METHOD OF PRODUCTION THEREOF

Title (de)

DRAM-ZELLENANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Title (fr)

ENSEMBLE DE CELLULES DE MEMOIRE VIVE DYNAMIQUE ET SON PROCEDE DE PRODUCTION

Publication

EP 1064682 A1 (DE)

Application

EP 99916756 A

Priority

  • DE 9900510 W
  • DE 19811882 A

Abstract (en)

[origin: DE19811882A1] The DRAM cell arrangement has a semiconductor structure (Sat) in which are arranged a first source/drain region and a channel region of at least one vertical MOS transistor of a memory cell. The source/drain region and the channel region are bounded at least by a first edge of the semiconductor structure. At least the first edge of the semiconductor structure is provided with a gate dielectric (GDa) at least in the region of the channel region of the MOS transistor. A gate electrode (Gaa) lies against the dielectric. The gate electrode is electrically connected to a first word line. An element which prevents formation of a channel is bounded by a second edge of the structure. A second word line runs along the second edge of the semiconductor structure. The first source/drain region of the MOS transistor is electrically connected to a first capacitor electrode of a capacitor. A second capacitor electrode of the capacitor is arranged over the first electrode. The second electrode is electrically connected to a bit line which runs perpendicular to the first word line.

IPC 1-7 (main, further and additional classification)

H01L 27/108; H01L 21/8242

IPC 8 full level (invention and additional information)

H01L 21/8242 (2006.01); H01L 27/108 (2006.01)

CPC (invention and additional information)

H01L 27/10852 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); Y10S 257/906 (2013.01); Y10S 257/907 (2013.01)

Citation (search report)

See references of WO 9948151A1

Designated contracting state (EPC)

DE FR GB IE IT

EPO simple patent family

DE 19811882 A1 19990923; EP 1064682 A1 20010103; JP 2002507841 A 20020312; TW 409409 B 20001021; US 6097049 A 20000801; WO 9948151 A1 19990923

INPADOC legal status


2009-07-08 [18R] REFUSED

- Ref Legal Event Code: 18R

- Effective date: 20090223

2008-04-23 [17Q] FIRST EXAMINATION REPORT

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- Effective date: 20080327

2001-01-03 [17P] REQUEST FOR EXAMINATION FILED

- Ref Legal Event Code: 17P

- Effective date: 20000908

2001-01-03 [AK] DESIGNATED CONTRACTING STATES:

- Ref Legal Event Code: AK

- Designated State(s): DE FR GB IE IT