EP 1076916 A1 20010221 - FLASH MEMORY CELL WITH SELF-ALIGNED GATES AND FABRICATION PROCESS
Title (en)
FLASH MEMORY CELL WITH SELF-ALIGNED GATES AND FABRICATION PROCESS
Title (de)
FLASH-SPEICHERZELLE MIT SELBST-JUSTIERTEN TOREN UND HERSTELLUNGSVERFAHREN
Title (fr)
CELLULE DE MEMOIRE FLASH A GRILLES AUTO-ALIGNEES ET SON PROCEDE DE FABRICATION
Publication
Application
Priority
- US 0004455 W 20000217
- US 25536099 A 19990223
- US 27567099 A 19990324
- US 31046099 A 19990512
Abstract (en)
[origin: WO0051188A1] Nonvolatile memory cell and process in which isolation oxide regions are formed on opposite sides of an active area in a substrate to a height above the substrate on the order of 80 to 160 percent of the width of the active area, a first layer of silicon is deposited on the gate oxide and along the sides of the isolation oxide regions to form a floating gate having a bottom wall which is substantially coextensive with the gate oxide and side walls having a height on the order of 80 to 160 percent of the width of the bottom wall, a dielectric film is formed on the floating gate, and a second layer of silicon is deposited on the dielectric film and patterned to form a control gate.
IPC 1-7
IPC 8 full level
H01L 21/28 (2006.01); H01L 21/8247 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01)
CPC (source: EP)
H01L 29/40114 (2019.07); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/7883 (2013.01); H10B 41/30 (2023.02); H10B 69/00 (2023.02)
Citation (search report)
See references of WO 0051188A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
WO 0051188 A1 20000831; CN 1300444 A 20010620; CN 1323440 C 20070627; EP 1076916 A1 20010221; JP 2002538608 A 20021112; TW 439280 B 20010607
DOCDB simple family (application)
US 0004455 W 20000217; CN 00800528 A 20000217; EP 00908762 A 20000217; JP 2000601695 A 20000217; TW 89102860 A 20000218