EP 1078462 A1 20010228 - GLOBAL SIGNAL DISTRIBUTION ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
Title (en)
GLOBAL SIGNAL DISTRIBUTION ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
Title (de)
ARCHITEKTUR ZUR VERTEILUNG VON GLOBALEN SIGNALENIN EINEM NUTZERPROGRAMMIERBAREN GATTERFELD
Title (fr)
ARCHITECTURE DE DISTRIBUTION D'UN SIGNAL GLOBAL DANS UN RESEAU DE PORTES PROGRAMMABLE PAR L'UTILISATEUR
Publication
Application
Priority
- US 0004477 W 20000222
- US 25506099 A 19990222
Abstract (en)
[origin: WO0049718A1] A global signal distribution architecture for an FPGA architecture that has a plurality of multiplexers (80) with inputs and an output. The outputs of the plurality of multiplexers (80) are coupled to global I/O lines (16) that are coupled to a global signal distribution bus (18) spanning a highest level in the FPGA architecture. A plurality of switch matrices (106) are coupled to global signal distribution bus (18) and to a plurality of utility conductors (108) that are coupled to at least one multiplexer associated with a lowest level in the FPGA architecture.
IPC 1-7
IPC 8 full level
H03K 19/177 (2006.01)
CPC (source: EP)
H03K 19/17736 (2013.01)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
WO 0049718 A1 20000824; WO 0049718 A9 20020627; EP 1078462 A1 20010228; EP 1078462 A4 20010613
DOCDB simple family (application)
US 0004477 W 20000222; EP 00913563 A 20000222