Global Patent Index - EP 1095481 A1

EP 1095481 A1 2001-05-02 - APPARATUS AND METHOD FOR REDUCING CLOCK SIGNAL PHASE SKEW IN A MASTER-SLAVE SYSTEM WITH MULTIPLE LATENT CLOCK CYCLES

Title (en)

APPARATUS AND METHOD FOR REDUCING CLOCK SIGNAL PHASE SKEW IN A MASTER-SLAVE SYSTEM WITH MULTIPLE LATENT CLOCK CYCLES

Title (de)

VERFAHREN UND VORRICHTUNG ZUR VERMINDERUNG DER TAKTSIGNALVERSCHIEBUNG IN EINEM MUSTER-SLAVE SYSTEM MIT MEHREREN VERBORGEN TAKTZYKLEN

Title (fr)

APPAREIL ET PROCEDE PERMETTANT DE REDUIRE L'EFFET D'OBLIQUITE DANS UN SYSTEME DISPOSITIF MAITRE-DISPOSITIF ASSERVI AVEC DE MULTIPLES CYCLES D'HORLOGE LATENTS

Publication

EP 1095481 A1 (EN)

Application

EP 00932161 A

Priority

  • US 0012488 W
  • US 30689799 A

Abstract (en)

[origin: WO0069109A1] A digital system includes a master device, a set of slave devices, and a clock generator to generate a clock signal. A transmission channel includes a clock-to-master path extending from the clock generator, through the set of slave devices, to the master device. The transmission channel also includes a clock-from-master path extending from the master device and through the set of slave devices. The transmission channel also includes a slave-to-master path positioned between a first slave device of the set of slave devices and the master device. A master-to-slave path is positioned between the master device and the first slave device. The cumulative length of the slave-to-master path and the master-to-slave path creates a master routing phase shift between a clock signal on the clock-to-master path and a clock signal on the clock-from-master path. A first lead samples the clock signal on the slave-to-master path. A second lead samples the clock signal on the master-to-slave path. A clock latency adjustment circuit is connected to the first lead and the second lead to produce an adjusted clock signal on the master-to-slave path to compensate for the master routing phase shift.

IPC 1-7 (main, further and additional classification)

G06F 1/10; H03L 7/081

IPC 8 full level (invention and additional information)

G06F 1/10 (2006.01); H03L 7/081 (2006.01); H04J 3/06 (2006.01); H04L 7/033 (2006.01)

CPC (invention and additional information)

H03L 7/0812 (2013.01); G06F 1/10 (2013.01); H04L 7/033 (2013.01)

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 0069109 A1 20001116; AT 398307 T 20080715; DE 60039153 D1 20080724; EP 1095481 A1 20010502; EP 1095481 A4 20051228; EP 1095481 B1 20080611; US 6426984 B1 20020730

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