Global Patent Index - EP 1097471 A1

EP 1097471 A1 2001-05-09 - INTEGRATED CIRCUIT WITH AT LEAST ONE TRANSISTOR AND A CAPACITOR AND CORRESPONDING PRODUCTION METHOD

Title (en)

INTEGRATED CIRCUIT WITH AT LEAST ONE TRANSISTOR AND A CAPACITOR AND CORRESPONDING PRODUCTION METHOD

Title (de)

INTEGRIERTE SCHALTUNGSANORDNUNG MIT MINDESTENS EINEM TRANSISTOR UND EINEM KONDENSATOR UND VERFAHREN ZU DEREN HERSTELLUNG

Title (fr)

CIRCUIT INTEGRE COMPORTANT AU MOINS UN TRANSISTOR ET UN CONDENSATEUR, ET SON PROCEDE DE PRODUCTION

Publication

EP 1097471 A1 (DE)

Application

EP 99936280 A

Priority

  • DE 9901501 W
  • DE 19822500 A

Abstract (en)

[origin: WO9960608A2] A structured conductive layer (L) and a structure, by means of which the transistor can be controlled, e.g. a word line (W), are arranged on top of each other. A vertical conductive structure (S), e.g. a spacer, connects a first source/drain zone (S/D1) of the transistor to the conductive layer (L), both of which form a first capacitor electrode having a large effective surface with higher packing density. A capacitor dielectric (KD) and a second capacitor electrode (P2) placed on top thereof are arranged above the vertical conductive structure (S) and the conductive layer (L). The transistor can be a vertical transistor. The vertical conductive structure (S) can be arranged on a first flank (F1) of the first source/drain zone (S/D1) and a gate electrode of the transistor can be mounted on a bordering second flank of the source/drain zone (S/D1). The circuit can be a DRAM cell array in which channel stop structures are arranged on the first flank of the first trenches, gate electrodes are arranged on the second flanks of the first trenches and vertical conductive structures are arranged on the second trenches (G2) and in which the word lines (W) extend between the second trenches (G2).

IPC 1-7 (main, further and additional classification)

H01L 21/00

IPC 8 full level (invention and additional information)

H01L 21/00 (2006.01); H01L 21/8242 (2006.01); H01L 27/108 (2006.01)

CPC (invention and additional information)

H01L 27/10852 (2013.01); H01L 27/10808 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01)

Citation (search report)

See references of WO 9960608A3

Designated contracting state (EPC)

DE

EPO simple patent family

WO 9960608 A2 19991125; WO 9960608 A3 20021024; DE 59914711 D1 20080508; EP 1097471 A1 20010509; EP 1097471 B1 20080326; TW 428313 B 20010401; US 6593614 B1 20030715

INPADOC legal status


2010-06-30 [PG25 DE] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

- Ref Country Code: DE

- Free text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

- Effective date: 20091201

2009-03-04 [26N] NO OPPOSITION FILED

- Effective date: 20081230

2008-10-31 [PGFP DE] POSTGRANT: ANNUAL FEES PAID TO NATIONAL OFFICE

- Ref Country Code: DE

- Payment date: 20080715

- Year of fee payment: 10

2008-05-08 [REF] CORRESPONDS TO:

- Document: DE 59914711 P 20080508

2008-03-26 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: B1

- Designated State(s): DE

2007-10-24 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: H01L 21/00 20060101AFI20070918BHEP

2007-10-24 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: H01L 27/108 20060101ALI20070918BHEP

2007-10-24 [RIC1] CLASSIFICATION (CORRECTION)

- IPC: H01L 21/8242 20060101ALI20070918BHEP

2006-09-27 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20060823

2002-12-11 [D17D] PUBLICATION OF THE DEFERRED SEARCH REPORT (DELETED)

2001-05-09 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20001025

2001-05-09 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): DE