EP 1099311 A1 20010516 - DELAY COMPENSATION FOR ANALOG-TO-DIGITAL CONVERTER IN SIGMA-DELTA MODULATORS
Title (en)
DELAY COMPENSATION FOR ANALOG-TO-DIGITAL CONVERTER IN SIGMA-DELTA MODULATORS
Title (de)
VERZÖGERUNGSKOMPENSATION DES A/D WANDLERS IN SIGMA-DELTA MODULATOREN
Title (fr)
COMPENSATION DU RETARD DU CONVERTISSEUR ANALOGIQUE-NUMERIQUE DANS LES MODULATEURS SIGMA-DELTA
Publication
Application
Priority
- FR 9902579 W 19991022
- FR 9813324 A 19981023
Abstract (en)
[origin: FR2785109A1] The sigma-delta modulator comprises an amplifying unit (10), a subtractor (20), a sample-and-hold device (30), an analog-to-digital converter (40), and a decoupling filter (50) in the direct chain. A compensating filter (70) is connected between the input of analog-to-digital converter (40) and the inverting input of the subtractor (20). A digital-to-analog converter (60) is connected to the inverting input of the amplifying unit (10). The amplifying unit (10) comprises an amplification stage with gain (G) greater than unity, preferably greater than hundred. The pulse response (RI) at the subtractor output comprises a first part covering the interval (0,T), where T is greater than the propagation delay, and a second part covering the interval T to infinity. The compensating filter (70) contributes to the first part, and the amplifying unit (10) contributes to the second part only. The compensating filter contributes to the second part of the pulse response (RI) in a manner as having a gain (K) so that the compensation in the useful frequency zone is at minimum. The sample-and-hold device (30) is controlled by the sampling frequency. The compensating filter (70) contains four sample-and-hold devices connected in series, branches with resistors, and an inverter in one branch. The instants of sampling are selected so that the compensating filter contributes to the first part of the pulse response with avoiding voltage surges at the input of the sample-and-hold device. The amplifying unit (10) also contains an integration stage, and a filter so that the gain is a function of frequency.
IPC 1-7
IPC 8 full level
H03M 3/02 (2006.01)
CPC (source: EP US)
H03M 3/37 (2013.01 - EP US); H03M 3/458 (2013.01 - EP US)
Citation (search report)
See references of WO 0025428A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
FR 2785109 A1 20000428; FR 2785109 B1 20010119; CA 2347164 A1 20000504; DE 69901037 D1 20020418; DE 69901037 T2 20021121; EP 1099311 A1 20010516; EP 1099311 B1 20020313; JP 2002528989 A 20020903; US 6388601 B1 20020514; WO 0025428 A1 20000504
DOCDB simple family (application)
FR 9813324 A 19981023; CA 2347164 A 19991022; DE 69901037 T 19991022; EP 99950814 A 19991022; FR 9902579 W 19991022; JP 2000578910 A 19991022; US 83015001 A 20010423