Global Patent Index - EP 1101389 A2

EP 1101389 A2 2001-05-23 - METHOD FOR PRODUCING AN INTEGRATED CIRCUIT COMPRISING A CAVITY IN A MATERIAL LAYER AND INTEGRATED CIRCUIT PRODUCED USING SAID METHOD

Title (en)

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT COMPRISING A CAVITY IN A MATERIAL LAYER AND INTEGRATED CIRCUIT PRODUCED USING SAID METHOD

Title (de)

VERFAHREN ZUR HERSTELLUNG EINER INTEGRIERTEN SCHALTUNGSANORDNUNG UMFASSEND EINEN HOHLRAUM IN EINER MATERIALSCHICHT, SOWIE EINE DURCH DAS VERFAHREN ERZEUGTE INTEGRIERTE SCHALTUNGSANORDNUNG

Title (fr)

PROCEDE PERMETTANT DE FORMER UN CIRCUIT INTEGRE COMPRENANT UNE CAVITE DANS UNE COUCHE DE MATERIAU ET CIRCUIT INTEGRE FABRIQUE SELON LEDIT PROCEDE

Publication

EP 1101389 A2 (DE)

Application

EP 99945888 A

Priority

  • DE 9902041 W
  • DE 19830535 A

Abstract (en)

[origin: WO0003560A2] The recess is produced in a material layer (S) by creating at least a first (S1) and a second structure (S2) in various steps. Said layers define each other laterally and extend to the bottom of the recess. The first structure (S1) and the second structure (S2) are so narrow that they can be made by creating conformally produced layers (F1, F2) that have an independent thickness and are smaller than the depth of said recess. The conformally produced layers (F1, F2) are formed in an appropriate deposition process. A covering structure can be produced on top of the first (S1) and second structure (S2). An opening can be made in said covering structure, through which the first structure (S1) and the second structure (S2) can be removed in an etching step.

IPC 1-7 (main, further and additional classification)

H04R 19/00; H01L 21/3105; H01L 21/762

IPC 8 full level (invention and additional information)

G01P 15/08 (2006.01); G01L 9/00 (2006.01); H01L 29/84 (2006.01); H04R 19/00 (2006.01); H04R 19/04 (2006.01); H04R 31/00 (2006.01)

CPC (invention and additional information)

H04R 19/00 (2013.01)

Citation (search report)

See references of WO 0003560A3

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 0003560 A2 20000120; WO 0003560 A3 20000224; AT 409398 T 20081015; DE 59914876 D1 20081106; EP 1101389 A2 20010523; EP 1101389 B1 20080924; JP 2002520862 A 20020709; US 2001005032 A1 20010628; US 6724058 B2 20040420

INPADOC legal status


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2008-03-26 [RTI1] TITLE (CORRECTION)

- Free text: METHOD FOR PRODUCING AN INTEGRATED CIRCUIT COMPRISING A CAVITY IN A MATERIAL LAYER AND INTEGRATED CIRCUIT PRODUCED USING SAID METHOD

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