EP 1130776 A2 20010905 - Load equalization in digital delay interpolators
Title (en)
Load equalization in digital delay interpolators
Title (de)
Lastausgleichung in digitalen Verzögerungsschaltungen mit Interpolation
Title (fr)
Egalisation de charge dans circuits de retard numériques avec interpolation
Publication
Application
Priority
- US 18578400 P 20000229
- US 75580601 A 20010105
Abstract (en)
A digital delay interpolator for receiving a first clock signal and a second clock signal, the second clock signal having a transition at a time that is delayed with respect to the time of a transition of the first clock signal, and for providing an output clock signal having a transition at a time intermediate the time of the transition of the first clock signal and the time of the transition of the second clock signal. The interpolator includes a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, the first plurality of delay circuits having an input port for receiving the first clock signal, and the second plurality of delay circuits having an input port being adapted to receive the second clock signal. The first plurality of delay circuits and the second plurality of delay circuits have outputs connected together to form the output of the digital delay interpolator. Each of the delay circuits includes a first delay buffer element for receiving one of the first and second clock signals, and being enabled by an enable signal, a second delay buffer element connected to the output of the first delay buffer, and being enabled by the enable signal, and circuit means for providing a predetermined voltage at the common connection point of the first delay buffer and the second delay buffer when the first and second delay buffers are not enabled. In another aspect of the invention, there is provided a tristatable element circuit being powered by a power supply connected to a ground connection and having a supply voltage. Included are a first tristatable circuit element having an input port, an output port and a tristate control port, and a second tristatable circuit element having an input port connected to the output port of the first tristatable circuit element, an output port and a tristate control port. Also provided is a switch coupled between the common connection node of the output of the first tristatable circuit element and the input of the second tristatable circuit element and a voltage source having a magnitude intermediate the supply voltage and ground, and being adapted to be switched to an ON state when the enable signal is OFF.
IPC 1-7
IPC 8 full level
H03K 5/13 (2006.01); H03K 19/003 (2006.01); H03L 7/081 (2006.01); H03K 5/00 (2006.01)
CPC (source: EP US)
H03K 5/133 (2013.01 - EP US); H03K 19/00384 (2013.01 - EP US); H03L 7/0814 (2013.01 - EP US); H03K 2005/00058 (2013.01 - EP US)
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
DOCDB simple family (publication)
EP 1130776 A2 20010905; EP 1130776 A3 20060215; EP 1130776 B1 20071226; AT E382206 T1 20080115; DE 60132038 D1 20080207; DE 60132038 T2 20081211; JP 2001285042 A 20011012; US 2001030566 A1 20011018; US 6377102 B2 20020423
DOCDB simple family (application)
EP 01200733 A 20010228; AT 01200733 T 20010228; DE 60132038 T 20010228; JP 2001054983 A 20010228; US 75580601 A 20010105