EP 1145301 A3 20020320 - CONDUCTOR TRACK SUPPORTING LAYER FOR LAMINATING INSIDE A CHIP CARD, CHIP CARD COMPRISING A CONDUCTOR TRACK SUPPORTING LAYER, AND METHOD FOR PRODUCING A CHIP CARD
Title (en)
CONDUCTOR TRACK SUPPORTING LAYER FOR LAMINATING INSIDE A CHIP CARD, CHIP CARD COMPRISING A CONDUCTOR TRACK SUPPORTING LAYER, AND METHOD FOR PRODUCING A CHIP CARD
Title (de)
LEITERBAHNTRÄGERSCHICHT ZUR EINLAMINIERUNG IN EINE CHIPKARTE, CHIPKARTE MIT EINER LEITERBAHNTRÄGERSCHICHT UND VERFAHREN ZUR HERSTELLUNG EINER CHIPKARTE
Title (fr)
COUCHE DE SUPPORT POUR PISTE CONDUCTRICE DESTINEE A ETRE STRATIFIEE DANS UNE CARTE A PUCE, CARTE A PUCE DOTEE DE LADITE COUCHE DE SUPPORT ET PROCEDE DE FABRICATION D'UNE CARTE A PUCE
Publication
Application
Priority
- DE 0002889 W 20000824
- DE 19940480 A 19990826
Abstract (en)
[origin: DE19940480A1] The invention relates to a conductor track supporting layer (1) for laminating inside a chip card comprising at least one conductor track (2), which is applied to the conductor track supporting layer (1) during a screen printing method and which is made of a screen printing paste, and comprising connecting areas (3) that are connected to the conductor track (2). According to the invention, the conductor track supporting layer has indentations (4a, 4b, 4c) which are located in the area of the connecting areas (3) and which are filled with the screen printing paste during the screen printing process. By using these inventive measures, it is possible to produce conductor track supporting layers provided with connecting areas of varying thicknesses. Conductor track supporting layers of this type enable the production of recesses in the chip cards after said conductor track supporting layers are laminated in chip cards. These recesses expose the connecting areas (3) for connection to electronic components, and the sensitive strip conductors (2) also located in the chip card are prevented from becoming damaged. The invention also relates to a chip card provided with the above-mentioned conductor track supporting layer and to a method for producing a chip card of this type.
IPC 1-7
IPC 8 full level
G06K 19/077 (2006.01); H05K 1/18 (2006.01); H05K 3/40 (2006.01); H05K 1/11 (2006.01); H05K 3/10 (2006.01)
CPC (source: EP US)
G06K 19/077 (2013.01 - EP US); G06K 19/07743 (2013.01 - EP US); H05K 1/183 (2013.01 - EP US); H05K 3/4069 (2013.01 - EP US); H05K 1/113 (2013.01 - EP US); H05K 3/107 (2013.01 - EP US); H05K 2201/09036 (2013.01 - EP US); H05K 2203/0156 (2013.01 - EP US)
Citation (search report)
See references of WO 0117011A2
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT
DOCDB simple family (publication)
DE 19940480 A1 20010308; DE 19940480 C2 20010613; AU 7642600 A 20010326; EP 1145301 A2 20011017; EP 1145301 A3 20020320; US 6783077 B1 20040831; WO 0117011 A2 20010308; WO 0117011 A3 20020110
DOCDB simple family (application)
DE 19940480 A 19990826; AU 7642600 A 20000824; DE 0002889 W 20000824; EP 00965786 A 20000824; US 6941902 A 20020412