Global Patent Index - EP 1161770 A1

EP 1161770 A1 2001-12-12 - DRAM CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

Title (en)

DRAM CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME

Title (de)

DRAM-ZELLENANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Title (fr)

AGENCEMENT DE CELLULES DE MEMOIRE RAM DYNAMIQUE, ET SON PROCEDE DE REALISATION

Publication

EP 1161770 A1 (DE)

Application

EP 00916811 A

Priority

  • DE 0000756 W
  • DE 19911148 A

Abstract (en)

[origin: DE19911148C1] A DRAM cell array, with single vertical transistor memory cells having buried bit lines and low space requirement, is new. A DRAM cell array, in which each memory cell consists of a vertical transistor and a capacitor, comprises: (a) a substrate (1) with parallel trenches, each containing a bit line in its lower portion; (b) a stripe-like recess which extends parallel to the trench on a first side wall of the trench lower portion and which is provided with insulation between the bit line and the substrate; (c) a further insulation on the upper trench side walls and the upper face of the bit line; (d) word lines (W) extending transversely to the bit lines and separated from the substrate by an insulating layer (I1); (e) alternating word line cuffs and insulating structures arranged over the bit lines in the trenches; (f) upper (S/Do) and lower transistor source/drain regions arranged between the trenches and under the word lines (W); (g) further insulating structures (I6) in the substrate for separating the upper source/drain regions (S/Do) of adjacent transistors; and (h) memory cell capacitors connected to the upper source/drain regions (S/Do). An Independent claim is also included for production of the above DRAM cell array.

IPC 1-7 (main, further and additional classification)

H01L 21/8242; H01L 27/108

IPC 8 full level (invention and additional information)

H01L 21/8242 (2006.01); H01L 27/108 (2006.01)

CPC (invention and additional information)

H01L 27/10876 (2013.01); H01L 27/10808 (2013.01); H01L 27/10823 (2013.01)

Citation (search report)

See references of WO 0055904A1

Designated contracting state (EPC)

DE FR GB IE IT

EPO simple patent family

DE 19911148 C1 20000518; CN 1150612 C 20040519; CN 1343371 A 20020403; EP 1161770 A1 20011212; JP 2002539642 A 20021119; JP 3786836 B2 20060614; KR 100403442 B1 20031030; KR 20010104379 A 20011124; TW 461086 B 20011021; US 2002079527 A1 20020627; US 6504200 B2 20030107; WO 0055904 A1 20000921

INPADOC legal status


2010-02-24 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20090902

2004-05-12 [RBV] DESIGNATED CONTRACTING STATES (CORRECTION):

- Designated State(s): DE FR GB IE IT

2001-12-12 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20010813

2001-12-12 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE