Global Patent Index - EP 1162741 A2

EP 1162741 A2 2001-12-12 - Adiabatic charging register circuit

Title (en)

Adiabatic charging register circuit

Title (de)

Registerschaltung mit adiabatischer Ladung

Title (fr)

Circuit de régistre à charge adiabatique

Publication

EP 1162741 A2 (EN)

Application

EP 01410063 A

Priority

JP 2000168846 A

Abstract (en)

An adiabatic charging register circuit (10) comprising a plurality of n-channel MOSFET's and a plurality of p-channel MOSFET's, is operated by a clock signal (PCK) which has a gradually rising and a gradually falling waveform generated by using a charge recycle power source in which charge supplied to a load is at least partially collected to said charge recycle power source, and following inequality is satisfied; <DF><FENCE TYPE=BAR>VTN</FENCE> + <FENCE TYPE=BAR>VTP</FENCE> ≥ VDD </DF> where VTN is threshold of an n-channel MOSFET, VTP is threshold of a p-channel MOSFET, and VDD is output voltage of said charge recycle power source. <IMAGE>

IPC 1-7 (main, further and additional classification)

H03K 3/012

IPC 8 full level (invention and additional information)

H03K 3/037 (2006.01); H03K 3/012 (2006.01)

CPC (invention and additional information)

H03K 3/012 (2013.01); H03K 3/037 (2013.01)

Citation (applicant)

JIN-CHEON KIM ET AL.: "A Low-Power Half-Swing Cloking Scheme for Flip-flop with Complementary Gate and Source Drive", IEICE TRANS.ELECTRON, September 1999 (1999-09-01)

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

EP 1162741 A2 20011212; EP 1162741 A3 20050323; EP 1162741 B1 20080716; DE 60134813 D1 20080828; JP 2001345680 A 20011214; JP 3632151 B2 20050323; US 2002000862 A1 20020103; US 2004189365 A1 20040930; US 6788121 B2 20040907; US 7030672 B2 20060418

INPADOC legal status


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