EP 1166362 A1 20020102 - NOVEL SEMICONDUCTOR DEVICE COMBINING THE ADVANTAGES OF SOLID AND SOI ARCHITECTURES, AND METHOD FOR MAKING SAME
Title (en)
NOVEL SEMICONDUCTOR DEVICE COMBINING THE ADVANTAGES OF SOLID AND SOI ARCHITECTURES, AND METHOD FOR MAKING SAME
Title (de)
NEUES HALBLEITERBAUELEMENT, DAS DIE VORTEILE DER MASSEN- UND SOI-ARCHITEKTUR KOMBINIERT, UND DESSEN HERSTELLUNGSVERFAHREN
Title (fr)
NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET SOI, ET PROCEDE DE FABRICATION
Publication
Application
Priority
- FR 0000641 W 20000316
- FR 9903470 A 19990319
Abstract (en)
[origin: FR2791178A1] The invention concerns a device comprising a silicon substrate (1) having a top surface coated with a thin gate dielectric layer (4) and wherein are formed source and drain regions (5, 6) defining between them a channel region (1a), a gate (7) on the thin gate dielectric layer (4) above the channel (1a) region. The invention is characterised in that it comprises in the channel region(1a) a continuous or discontinuous insulating cavity (2) defining with the source and drain regions a thin silicon layer (3) 1 to 50 nm thick located above the insulating cavity, said insulating cavity (2) having a length representing at least 70 % of a predetermined minimum channel length. The invention is applicable to MOSFET transistors.
IPC 1-7
IPC 8 full level
H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01)
CPC (source: EP)
H01L 29/0649 (2013.01); H01L 29/66772 (2013.01); H01L 29/78603 (2013.01); H01L 29/78654 (2013.01)
Citation (search report)
See references of WO 0057480A1
Designated contracting state (EPC)
GB IT
DOCDB simple family (publication)
FR 2791178 A1 20000922; FR 2791178 B1 20011116; EP 1166362 A1 20020102; WO 0057480 A1 20000928
DOCDB simple family (application)
FR 9903470 A 19990319; EP 00910964 A 20000316; FR 0000641 W 20000316