Global Patent Index - EP 1186044 A1

EP 1186044 A1 20020313 - MEMORY CELL UNIT AND METHOD OF PRODUCING SAME

Title (en)

MEMORY CELL UNIT AND METHOD OF PRODUCING SAME

Title (de)

SPEICHERZELLENANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Title (fr)

ENSEMBLE CELLULES MEMOIRES ET SON PROCEDE DE PRODUCTION

Publication

EP 1186044 A1 20020313 (DE)

Application

EP 00926688 A 20000324

Priority

  • DE 0000906 W 20000324
  • DE 19914496 A 19990330

Abstract (en)

[origin: DE19914496A1] A memory cell structure comprises a contact (K) within a substrate (S) for connecting a capacitor and a MOS transistor on opposite substrate surfaces (O1, O2). A memory cell structure comprises a MOS transistor connected to a bit line (B) on one substrate surface (O1), a capacitor on the opposite substrate surface (O2) and a contact (K) in the substrate (S) for connecting the capacitor with the MOS transistor. An Independent claim is also included for production of the above memory cell structure.

IPC 1-7

H01L 27/108; H01L 21/8242

IPC 8 full level

H01L 21/8242 (2006.01); H01L 21/8246 (2006.01); H01L 27/105 (2006.01); H01L 27/108 (2006.01)

CPC (source: EP KR)

H01L 27/108 (2013.01 - KR); H01L 27/10864 (2013.01 - EP); H01L 27/10867 (2013.01 - EP); H01L 27/1087 (2013.01 - EP)

Citation (search report)

See references of WO 0060666A1

Designated contracting state (EPC)

DE FR GB IE IT

DOCDB simple family (publication)

DE 19914496 A1 20001005; EP 1186044 A1 20020313; JP 2002541666 A 20021203; JP 3961223 B2 20070822; KR 100458988 B1 20041203; KR 20010110684 A 20011213; TW 479351 B 20020311; US 2002071320 A1 20020613; US 6518613 B2 20030211; WO 0060666 A1 20001012

DOCDB simple family (application)

DE 19914496 A 19990330; DE 0000906 W 20000324; EP 00926688 A 20000324; JP 2000610066 A 20000324; KR 20017012139 A 20010924; TW 89105587 A 20000327; US 96830401 A 20011001